CS5351

DS565PP2

3

Figure 4. Single Speed Mode Stopband Rejection ....................................................................... 14

Figure 5. Single Speed Mode Transition Band ............................................................................. 14

Figure 6. Single Speed Mode Transition Band (Detail)................................................................. 14

Figure 7. Single Speed Mode Passband Ripple ........................................................................... 14

Figure 8. Double Speed Mode Stopband Rejection...................................................................... 14

Figure 9. Double Speed Mode Transition Band ............................................................................ 14

Figure 10. Double Speed Mode Transition Band (Detail) ............................................................. 15

Figure 11. Double Speed Mode Passband Ripple ........................................................................ 15

Figure 12. Quad Speed Mode Stopband Rejection ...................................................................... 15

Figure 13. Quad Speed Mode Transition Band............................................................................. 15

Figure 14. Quad Speed Mode Transition Band (Detail) ................................................................ 15

Figure 15. Quad Speed Mode Passband Ripple........................................................................... 15

Figure 16. Master Mode, Left Justified SAI ................................................................................... 19

Figure 17. Slave Mode, Left Justified SAI ..................................................................................... 19

Figure 19. Slave Mode, I2S SAI .................................................................................................... 19

Figure 20. OVFL Output Timing .................................................................................................... 19

Figure 21. Left-Justified Serial Audio Interface ............................................................................. 20

Figure 22. I2S Serial Audio Interface............................................................................................. 20

Figure 23. OVFL Output Timing, I2S Format ................................................................................ 20

Figure 24. OVFL Output Timing, Left-Justified Format ................................................................. 20

Figure 25. CS5351/CS5361 Analog Input Buffer .......................................................................... 24

LIST OF TABLES

Table 1. CS5351 Mode Control ............................................................................................................. 6

Table 2. CS5351 Common Master Clock Frequencies ........................................................................ 7

Table 3. CS5351 Slave Mode Clock Ratios .......................................................................................... 8