CS5360 datasheet(13/22 Pages) CIRRUS

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CS5360

DS280PP2

4.2

Bar Graph Mode

This mode provides a decoded output format which

indicates the peak Peak Signal Level in a "Bar

Graph" format.

4.3

Overflow

Overflow indicates analog input overrange for the

Left and Right channels as of the last update re-

quest on the Peak Update pin. A value of 1 indi-

cates an overrange condition. The left channel

information is output on OVFL during the left

channel portion of LRCK. The right channel infor-

mation is available on OVFL during the right chan-

nel portion of LRCK.

4.4

Initialization

Upon initial power-up, the digital filters and delta-

sigma modulators are reset and the internal voltage

reference is powered down. The CS5360 will re-

main in the power-down mode until valid clocks

are presented. A valid MCLK is required to exit

power-down in Master Mode. However, in Slave

Mode, MCLK and LRCK of the proper ratio are re-

quired to exit power-down. MCLK occurrences are

also counted over one LRCK period to determine

the MCLK / LRCK frequency ratio in Slave Mode.

Power is then applied to the internal voltage refer-

ence, the analog inputs will move to approximately

2.2 V and output clocks will begin (Master Mode

only). This process requires 32 periods of LRCK

and is followed by the initialization sequence.

4.5

Initialization with High Pass Filter

Enabled

28,672 LRCK cycles are required for the initializa-

tion sequence with the high pass filter enabled.

This time is dominated by the settling time required

for the high pass filter.

4.6

Initialization and Internal

Calibration with High Pass Filter

Disabled

If the HP DEFEAT pin is high (high pass filter dis-

abled) during the initialization sequence, the

CS5360 will perform an internal dc calibration by:

1) disconnecting the internal ADC inputs from the

input pins,

2) connecting the (differential) ADC inputs to a

common reference voltage,

3) running the high pass filter with a fast settling

time constant,

4) freezing the dc offset register, and

5) reconnecting the internal ADC inputs to the in-

put pins.

This procedure takes 4,160 cycles of LRCK. Un-

like the system calibration procedure described in

the High Pass Filter section, a dc calibration per-

formed during start-up will only eliminate offsets

internal to the CS5360, and should result in output

codes which accurately reflect the differential dc

signal at the pins.

Input Level

P7 - P0

Overflow

11111111

0 dB to -3 dB

01111111

-3 dB to -6 dB

00111111

-6 dB to -10 dB

00011111

-10 dB to -20 dB

00001111

-20 dB to -30 dB

00000111

-30 dB to -40 dB

00000011

-40 dB to -60 dB

00000001

< - 60 dB

00000000

Table 4. P7 to P0 - Peak Signal Level Bits -Bar Graph

Mode

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