DATASHEET

LOW PHASE NOISE ZERO DELAY BUFFER

ICS571

IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER

1

ICS571

REV H 051310

Description

The ICS571 is a high speed, high output drive, low phase

noise Zero Delay Buffer (ZDB) which integrates IDT’s

proprietary analog/digital Phase Locked Loop (PLL)

techniques. IDT introduced the world standard for these

devices in 1992 with the debut of the AV9170, and updated

that with the ICS570. The ICS571, part of IDT’s

ClockBlocks™ family, was designed to operate at higher

frequencies, with faster rise and fall times, and with lower

phase noise. The zero delay feature means that the rising

edge of the input clock aligns with the rising edges of both

outputs, giving the appearance of no delay through the

device. There are two outputs on the chip, one being a

low-skew divide by two of the other.

The chip is ideal for synchronizing outputs in a large variety

of systems, from personal computers to data

communications to video. By allowing offchip feedback

paths, the ICS571 can eliminate the delay through other

devices. The use of dividers in the feedback path will enable

the part to multiply by more than two.

Features

MHz offset from carrier

TTL levels

Block Diagram