DS2406

25 of 30

READ/WRITE TIMING DIAGRAM (continued) Figure 15

Read-data Time Slot

RESISTOR

MASTER

DS2406

Master

Sampling Window

60 µs

≤ t

0V

*

The optimal sampling point for the master is as close as possible to the end time of the 15

µs t

RDV

of time for the pull-up resistor to recover the line to a high level. For a Read-zero time slot it

PROGRAM PULSE

To copy data from the 8-bit scratchpad to the EPROM data or status memory, a program pulse is applied

to the data line after the bus master has confirmed that the CRC for the current byte is correct. During

programming, the bus master controls the transition from a state where the data line is idling high via the

pull-up resistor to a state where the data line is actively driven to a programming voltage of 12 volts

providing a minimum of 10 mA of current to the DS2406. This programming voltage (Figure 16) should

be applied for 480 µs, after which the bus master should return the data line to the idle high state. Note

that due to the high voltage programming requirements for any 1-Wire EPROM device, it is not possible

to multi-drop non-EPROM based 1-Wire devices with the DS2406 during programming. An internal

diode within the non-EPROM based 1-Wire devices will attempt to clamp the data line at approximately

8 volts and could potentially damage these devices.