ASI4U / ASI4U-E / ASI4U-F

Spec. 3.0 Compliant Universal AS-I IC

Data Sheet

April 2, 2012

© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.2

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.

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List of Figures

Figure 1: Ptot = f(

Figure 2: ASI4U Package Pin Assignment.............................................................................................................. 6

Figure 3 Functional Block Diagram ......................................................................................................................... 6

Figure 7: Receiver comparator threshold set-up in principle ................................................................................... 6

Figure 8: Addressing Channel Input (IRD), Photo-current Waveforms.................................................................... 6

Figure 9: Timing Diagram Parameter Port P0 ... P3, PST ....................................................................................... 6

Figure 10: Timing diagram data port DO0 ... DO3, DI0 … DI3, DSR....................................................................... 6

Figure 12: Principle of input filtering........................................................................................................................ 6

Figure 13: Principle of AS-i cycle input filtering (exemplary for Slave with Address 1) ............................................ 6

Figure 14: Flowchart - Input D3 (D2,D1) in Safety Mode ........................................................................................ 6

Figure 15: Flowchart - Input D0 in Safety Mode...................................................................................................... 6

Figure 16: Flowchart - Data_Exchange_Disable ..................................................................................................... 6

Figure 17: Power-On Behavior (all modes) ............................................................................................................. 6

Figure 18: Timing diagram external Reset via DSR ................................................................................................ 6

Figure 19: Manchester-II-Modulation principle ........................................................................................................ 6

Figure 20: Standard Application circuit with bi-directional Data I/O......................................................................... 6

Figure 21: Extended power application circuit......................................................................................................... 6

Figure 22: ASI4U Master Mode Application ............................................................................................................ 6

Figure 23: SOP Package ........................................................................................................................................ 6

Figure 24: Package Dimensions ............................................................................................................................. 6

Figure 25: SSOP Package...................................................................................................................................... 6

Figure 26: Package Outline Dimensions ................................................................................................................. 6

Figure 27: Package Marking ................................................................................................................................... 6