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ZIOL2102 数据表(PDF) 43 Page - List of Unclassifed Manufacturers

部件名 ZIOL2102
功能描述  IO-Link compliant HV Line Driver IC Family
PDF  91 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

ZIOL2102 数据表(HTML) 43 Page - List of Unclassifed Manufacturers

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ZIOL2xxx – IC Family
IO-Link compliant HV Line Driver IC Family
Data Sheet
January 31, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
43 of 90
Reg.-Name
Addr.
Bit-Field
Bit Reset-
Value
r/w
Comment
Reference
14 WURQ_PAD_MODE
6
0
r/w
WURQ_PAD_MODE:
0 = open-drain /
1 = push-pull
14 DCDC_READY_DELAY
5
1
r/w
DCDC-Ready-delay-
enable / 0 = No delay
/ 1 = delay 50 ms
14 BOTH_CHANNEL_LOCK
4
0
r/w
lock only, when both
channel are in OVL-
alarm
Recommended to be
set (=1) in tandem
mode
14 IRQ_NOREG
3
0
r/w
0 = IRQ-Port follows
state-reg / 1 = IRQ
follows state-signals
14 WURQSOURCE
2
0
r/w
Source for WURQ-
detection 0 = COM /
1 = AUX
14 WURQDETECT_CURRENT
1
1
r/w
WURQ detection on
current (overload)
14 WURQDETECT_LVL
0
1
r/w
WURQ detection on
levels (can be
combined with
current)
AUX_LOCK_TIME
15
7:0
100
r/w
Overload: time until
Lock is released
Added in
Rev B
STATUS REGISTER
MON_RST_LOCK_WURQ 16
4:0
0
w/pulse
Figure 3.14
16 MON_RST_POWER_FAIL
4
0
w/pulse
Reset for power fail
due to line-fault or
under-voltage
Added in
Rev B
16 MON_RST_WURQ
3
0
w/pulse
Reset for Wake Up
Request
16 MON_RST_AUX_LOCK
2
0
w/pulse
Reset for Channel 2
Lock
16 MON_RST_COM_LOCK
1
0
w/pulse
Reset for Channel 1
Lock



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