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A3P015 数据表(PDF) 76 Page - Microsemi Corporation |
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A3P015 数据表(HTML) 76 Page - Microsemi Corporation |
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76 / 212 page ![]() ProASIC3 DC and Switching Characteristics 2- 70 R e v i sio n 1 4 Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear CLK Enable CLR Data_out Data Y AA EOUT DOUT Core Array DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR BB CC DD EE FF GG LL HH JJ KK INBUF INBUF CLKBUF Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered |
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