MA28151

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1.12 REQUEST TO SEND (

RTS)

The

RTS output signal is a general purpose, 1-bit inverting

output port. It can be set low by programming the appropriate

bit in the Command instruction word. The

RTS output signal is

normally used for modem control such as Request To Send.

1.13 CLEAR TO SEND (

CTS)

A low on this input enables the MA28151 to transmit serial

data if the Tx Enable bit in the Command byte is set to a high.

If either a Tx Enable off or

CTS off condition occurs while the

Tx is in operation, the Tx will transmit all the data in the

USART, written prior to Tx disable command, before shutting

down.

1.14 TRANSMITTER BUFFER

The Transmitter Buffer accepts parallel data from the Data

Bus Buffer, converts it to a serial bit stream, inserts the

appropriate characters or bits (based on the communication

technique) and outputs a composite serial stream of data on

the TxD output pin on the falling edge of

TxC. The transmitter

will begin transmission upon being enabled if

CTS = 0. The

TxD line will be held in the marking state immediately upon a

master Reset, or when Tx Enable or

CTS = 1, or the

transmitter is empty.

1.15 TRANSMITTER CONTROL

The Transmitter Control manages all activities associated

with the transmission of serial data. It accepts and issues

signals both externally and internally to accomplish this

function.

1.16 TRANSMITTER READY (TxRDY)

This output signals the CPU that the transmitter is ready to

accept a data character. The TxRDY output pin can be used as

an interrupt to the system since it is masked by TxEnable; or,

for Polled operation, the CPU can check TxRDY using a Status

Read operation. TxRDY is automatically reset by the falling

edge of DSN (with RDWN low) when a data character is

loaded from the CPU.

Note that when using the polled operation, the TxRDY

status bit is not masked by TxEnable, but will only indicate the

Empty/Full Status of the Tx Data input Register.

1.17 TRANSMITTER EMPTY (TxE)

When the MA28151 has no characters to send, the

TxEMPTY output will go high. It resets upon receiving a

character from CPU if the transmitter is enabled. TxEMPTY

remains high when the transmitter is disabled. TxEMPTY can

be used to indicate the end of transmission mode, so that the

CPU can turn the line around in the half-duplex operational

mode.

In the Synchronous mode, a high on the TxEMPTY output

indicates that a character has not been loaded and the SYNC

character or characters are about to be or are being

automatically transmitted as fillers. TxEMPTY does not go low

when the SYNC characters are being shifted out.

1.18 TRANSMITTER CLOCK

(TxC)

The Transmitter Clock controls the rate at which the

character is to be transmitted. In the Synchronous

transmission mode, the Baud Rate (1x) is equal to the

TxC

frequency. In Asynchronous transmission mode, the baud rate

is a fraction of the actual

TxC frequency. A portion of the mode

instruction selects this factor; it can be 1,1/16 or 1/64 the

TxC.

For Example:

If Baud Rate equals 110 Baud

TxC equals 110Hz in the 1x mode

TxC equals 1 72KHz in the 16x mode

TxC equals 7.04KHz in the 64x mode

The falling edge of

TxC shifts the serial data out of the

MA28151.

1.19 RECEIVER BUFFER

The Receiver accepts serial data, converts the data to

parallel format, checks for bits or characters that are unique to

the communications techniques and sends an assembled

character to the CPU. Serial data is input to the RxD pin and is

clocked in on the rising edge of RxC.

1.20 RECEIVER CONTROL

This functional block manages all receiver-related activities

which consist of the following features:

The RxD initialisation circuit prevents the MA28151 from

mistaking an unused input line for an active low data line in the

break condition. Before starting to receive serial characters on

the RxD line, a valid 1 must first be detected after a chip master

Reset. Once this has been determined, a search for a valid low

(start bit) is enabled. This feature is only active in the

asynchronous mode and is only done once for each master

Reset.

The False Start bit detection circuit prevents false starts as

the result of a transient noise spike by first detecting the falling

edge and then strobing the nominal center of the Start bit (RxD

= low).

Parity error detection sets the corresponding status bit.

The Framing Error status bit is set if the Stop bit is absent

at the end of the data byte (asynchronous mode).

1.21 RxRDY (RECEIVER READY)

This output indicates that the MA28151 contains a

character that is ready to be input to the CPU. RxRDY can be

connected to the interrupt structure of the CPU or, for polled

operation, the CPU can check the condition of RxRDY using a

Status Read operation. RxEnable, when off holds RxRDY in

the Reset Condition. For Asynchronous mode, to set RxRDY,

the Receiver must be enabled to sense a Start Bit and a

complete character must be assembled and transferred to the

Data Output Register. For Synchronous mode, to set RxRDY,