IXMS150PSI datasheet(4/10 Pages) IXYS

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IXMS 150

Functional Description

Introduction

The IXMS150 is designed with mono-

lithic CMOS technology. The IC is

primarily intended for use with two-

phase step motors in the microstepping

mode but may also be used for control

of two DC motors, audio amplifiers, or

any application requiring two synchro-

nized PWMs. The IXMS150 simulta-

neously controls the currents in each of

two separate H-bridges. This device

utilizes both analog and digital functions.

The IC has five fundamental sections:

(1) oscillator and feedforward circuitry,

(2) analog section for control of the

motor currents, (3) a protection network

to protect the H-bridges and the motor

from abnormal conditions, (4) the digital

PWM logic for the control signals, and

(5) the power supply section which

includes a negative bias generator.

Oscillator

The IXMS150 contains an internal

oscillator which is controlled by

adjusting the values of R

O and CO.

These two components determine the

switching frequency, amount of dead

time, and the minimum pulse width at

output pins 9, 10, 15 and 16. The

minimum and maximum values of R

and C

O are given in the Electrical

Characteristics.

The oscillator also sets the frequency of

the charge pump circuit in the internal

negative bias generator (V

BB). At lower

frequencies (<40 kHz) the value of

CPUMP must be increased to assure

proper operation.

Feedforward Compansation

In all fixed frequency PWM control

systems open loop gain, motor current

slew rate, and motor current ripple are

proportional to the motor supply

voltage. Gain variations due to supply

voltage changes complicate the design

of such systems and restrict their band-

width to the minimum worst case

condition. For this reason, an advanced

adaptive compensation scheme is built-

in using a feedforward technique. This

feature has been designed such that

open loop gain is inversely proportional

to the voltage applied to the FFWD pin,

normally a fraction of the motor supply.

As a result, open loop gain can be

made independent of the high voltage

supply and system bandwidth can be

maximized.

Analog Section

The analog section of each channel of

the IXMS150 consists of a signal

processor and an error amplifier. The

signal processor is required since the

voltage developed across the sense

resistor often contains transients asso-

ciated with the switching characteristics

of the power devices. These transients

need to be properly filtered for the

system to operate with the desired

degree of precision. Because of this,

the IXMS150 uses proprietary analog

and digital signal processing techni-

ques that sense the true average phase

currents. Since this requires only one

sense resistor per H-bridge it avoids

mismatches in charge/discharge

currents associated with two sense

resistor per H-bridge topologies.

The instantaneous difference between

the motor current and the control input

is integrated via the E/A amp and fed to

the PWM comparator to generate the

appropriate signals for the H-bridges.

External compensation of the input and

sense signals is provided for via the

comp1, comp2 and comp3 pins.

Protection Circuitry

The IC has a two-level Over/Excess

Current protection circuit. Maximum

current is represented as 0.625 V at the

SENSE input. If the SENSE voltage

exceeds 0.9 volts for more than one

microsecond, the switching outputs

(VOUT) and OUTDIS will be forced low.

This represents a current that is 40 %

beyond full scale. If the SENSE voltage

exceeds 3.6 V, these outputs will be

forced low immediately. This repre-

sents a current that is 500% beyond full

scale. The time delay on the lower level

of overcurrent avoids erroneous

shutdowns as a result of noise spikes

that are coupled from the motors H-

bridges. Note that the threshold

voltages cited here assume a supply of

+12 V.

Undervoltage Lockout

A third protection mechanism is the

Under-Voltage Lockout. It assures

proper behavior on power-up and

power-down and avoids high power

dissipation in the H-bridge due to

insufficient gate voltage. It uses a zener

for reference and has a trip point set at

8 V. It will also check to make sure

there is sufficient negative bias to

insure proper operation. This is typically

-1.6 V. OUTDIS will be held low by the

UV Lockout circuit until V

BB and VDD

reach these values.

Output Disable Feature

To enable external over-temperature

protection, the output disable pin

(OUTDIS) is available on the IXMS150.

When pulled low this disables the

output by forcing all output pins low.

The same output disable input pin is

also used as a status output. When it is

pulled low by the internal circuitry it

indicates an error condition such as

undervoltage (V

DD), insufficient negative

bias voltage (V

BB) or over/excess

current. This can be used as a status

indicator in smart systems.

PWM Section

The PWM comparator generates two

complementary signals based on the

output of the error amplifier. Dead-time

is then added which is adjusted by the

selection of the external oscillator

capacitor. There is also a minimum duty

cycle clamp circuit that allows the use

of an AC coupled H-bridge.

Supply Section

The main power supply (V

DD) is applied

to pin 24. This is typically +12 V. Internal

bias circuitry presents a V

DD/2 reference

voltage at pin 8, BYPASS. A 0.1 µF

capacitor should be connected from pin

8 to analog ground for noise immunity.

Negative Bias Generator

The IXMS150 samples both positive

and negative voltages at the motor

sense feedback resistor. In addition,

since errors in the input current around

zero are a major contributor to micro-

step positioning error, the input control

range is bipolar and specified as ±2 V

full scale. For these reasons it is desi-

rable to have both positive and nega-

tive power supplies. In order to enable

single 12 V supply operation, a negative

voltage generator and regulator are

built into the IC. This is a charge pump

circuit whose frequency is that of the

onboard oscillator. It utilizes an external

pair of capacitors and diodes to gene-

rate a negative bias equal to -V

DD/5 or

approximately -2.4 V for V

DD = 12 V.

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