数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

CS49611X 数据表(PDF) 13 Page - Cirrus Logic

部件名 CS49611X
功能描述  Digital Audio Networking Processor
PDF  54 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS49611X 数据表(HTML) 13 Page - Cirrus Logic

Back Button CS49611X Datasheet HTML 9Page - Cirrus Logic CS49611X Datasheet HTML 10Page - Cirrus Logic CS49611X Datasheet HTML 11Page - Cirrus Logic CS49611X Datasheet HTML 12Page - Cirrus Logic CS49611X Datasheet HTML 13Page - Cirrus Logic CS49611X Datasheet HTML 14Page - Cirrus Logic CS49611X Datasheet HTML 15Page - Cirrus Logic CS49611X Datasheet HTML 16Page - Cirrus Logic CS49611X Datasheet HTML 17Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 54 page
background image
CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
DS651UM23
©Copyright 2005 Cirrus Logic, Inc.
13
Version 2.3
4.2.3 Synchronous Serial (Audio) Signals
The synchronous serial interfaces are used to bring digital audio into and out of the
system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing
and format is described in "Digital Audio Interface" on page 19.
4.2.4 Audio Clock Signals
See "Synchronization" on page 17 for an overview of synchronization modes and issues.
*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out
implementation.
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
DAO1_SCLK
Audio Bit Clock
Out
J3:A7
20
Synchronous serial bit clock.
64 FS for CS18100x & CS49610x (2x1 channel)
64 FS for CS18101x & CS49611x (2x4
channels)
128 FS for CS18102x & CS49612x (4x4
channels)
Typically tied to DAI1_SCLK.
DAO1_DATA[3:0]
Audio Output
Data
Out
J3:A18,
B18
15-17, 19
Output synchronous serial audio data
DAO1_DATA[3:1] not used for CS18100x &
CS49610x.
DAI1_DATA[3:0]
Audio Input Data
In
J3:
A[15:12]
131, 132, 134, 135
Input synchronous serial audio data
DAI1_DATA[3:1] not used for CS18100x &
CS49610x.
DAI1_SCLK
Audio Bit Clock
In
J4:A7
137
Should be tied to DAO1_SCLK.
Synchronous serial bit clock.
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
DAI1_LRCLK
Sample clock
input
In
138
Should be tied to DAO1_LRCLK for all devices.
DAO1_LRCLK
(FS1)
Sample clock
output
Out
J3:A3
22
FS1 (word clock) for CS18100x/CS49610x and
CS18101x/CS49611x.
DAO2_LRCLK
(FS1)
Sample clock
output
Out
J3:A3
14
FS1 (word clock) for CS18102x & CS49612x.
REFCLK_IN
Reference clock
In
J3:A6
97
Clock input for synchronizing network to an
external clock source, for redundancy control
and synchronization of FS divider chain to
external source. See "Synchronization" on
page 17 for more detail.
MCLK_IN
Master audio
clock input
In
J3:A5
8*
For systems featuring multiple CobraNet
interfaces operating off a common master
clock. See "Synchronization" on page 17 for
more detail.
MCLK_OUT
Master audio
clock output
Out
J3:A4
8*
Low jitter 24.576 MHz master audio clock.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com