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AP2181 数据表(PDF) 4 Page - Diodes Incorporated |
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AP2181 数据表(HTML) 4 Page - Diodes Incorporated |
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4 / 17 page ![]() AP2181/ AP2191 Document number: DS31563 Rev. 7 - 2 4 of 17 www.diodes.com March 2013 © Diodes Incorporated AP2181/ AP2191 Electrical Characteristics (@TA = +25°C, VIN = +5V, unless otherwise specified.) Symbol Parameter Test Conditions Min Typ Max Unit VUVLO Input UVLO RLOAD = 1kΩ 1.6 1.9 2.5 V ISHDN Input Shutdown Current Disabled, IOUT = 0 0.5 1 A IQ Input Quiescent Current Enabled, IOUT = 0 45 70 µA ILEAK Input Leakage Current Disabled, OUT grounded 1 µA IREV Reverse Leakage Current Disabled, VIN = 0V, VOUT = 5V, IREV at VIN 1 µA RDS(ON) Switch On-Resistance VIN = 5V, IOUT= 1.5A TA = +25°C SOT25, MSOP-8EP, SO-8 95 115 m Ω U-DFN2018-6 90 110 -40 C ≤ TA ≤ +85°C 140 VIN = 3.3V, IOUT= 1.5A TA = +25°C 120 140 -40 C ≤ TA ≤ +85°C 170 ISHORT Short-Circuit Current Limit Enabled into short circuit, CL = 100µF 2.0 A ILIMIT Over-Load Current Limit VIN = 5V, VOUT = 4.5V, CL = 120µF, -40°C ≤ TA ≤ +85°C 1.6 2.1 2.6 A ITrig Current Limiting Trigger Threshold Output Current Slew Rate (<100A/s) , CL = 100µF 2.6 A VIL EN Input Logic Low Voltage VIN = 2.7V to 5.5V 0.8 V VIH EN Input Logic High Voltage VIN = 2.7V to 5.5V 2 V ISINK EN Input Leakage VEN = 5V 1 µA TD(ON) Output Turn-On delay time CL = 1µF, RLOAD = 10Ω 0.05 ms TR Output Turn-On rise time CL = 1µF, RLOAD = 10Ω 0.6 1.5 ms TD(OFF) Output Turn-Off delay time CL = 1µF, RLOAD = 10Ω 0.01 ms TF Output Turn-Off fall time CL = 1µF, RLOAD = 10Ω 0.05 0.1 ms RFLG FLG Output FET On-Resistance IFLG = 10mA, CL = 100µF 20 40 Ω TBlank FLG Blanking Time CIN = 10µF, CL = 100µF 4 7 15 ms TSHDN Thermal Shutdown Threshold Enabled, RLOAD = 1kΩ 140 C THYS Thermal Shutdown Hysteresis 25 C θJA Thermal Resistance Junction-to- Ambient SO-8 (Note 5) 110 C/W MSOP-8EP (Note 6) 60 C/W SOT25 (Note 7) 157 C/W U-DFN2018-6 (Note 8) 70 C/W Notes: 5. Test condition for SO-8: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout. 6. Test condition for MSOP-8EP: Device mounted on 2” x 2” FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer and thermal vias to bottom layer ground plane. 7. Test condition for SOT25: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout. 8. Test condition for U-DFN2018-6: Device mounted on FR-4 2-layer board, 2oz copper, with minimum recommended pad on top layer and 3 vias to bottom layer 1.0”x1.4” ground plane. |
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