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Data Sheet

AD7625

Rev. A | Page 19 of 24

DIGITAL INTERFACE

Conversion Control

All analog-to-digital conversions are controlled by the CNV

signal. This signal can be applied in the form of a CNV+/CNV−

LVDS signal, or it can be applied in the form of a 2.5 V CMOS

logic signal to the CNV+ pin. The conversion is initiated by the

rising edge of the CNV signal.

After the AD7625 is powered up, the first conversion result

generated is invalid. Subsequent conversion results are valid

provided that the time between conversions does not exceed

the maximum specification for tCYC.

The two methods for acquiring the digital data output of the

AD7625 via the LVDS interface are described in the following

sections.

Echoed-Clock Interface Mode

The digital operation of the AD7625 in echoed-clock interface

mode is shown in Figure 29. This interface mode, requiring

only a shift register on the digital host, can be used with many

digital hosts (FPGA, shift register, microprocessor, and so on).

It requires three LVDS pairs (D±, CLK±, and DCO±) between

each AD7625 and the digital host.

The clock DCO± is a buffered copy of CLK± and is synchronous

to the data, D±, which is updated on the falling edge of DCO+

(tD). By maintaining good propagation delay matching between

D± and DCO± through the board and the digital host, DCO±

can be used to latch D± with good timing margin for the shift

Conversions are initiated by a CNV± pulse. The CNV± pulse

must be returned low (≤tCNVH maximum) for valid operation.

After a conversion begins, it continues until completion. Addi-

tional CNV± pulses are ignored during the conversion phase.

After the time tMSB elapses, the host should begin to burst the

CLK±. Note that tMSB is the maximum time for the MSB of the

new conversion result and should be used as the gating device

for CLK±. The echoed clock, DCO±, and the data, D±, are

driven in phase, with D± being updated on the falling edge of

DCO+; the host should use the rising edge of DCO+ to capture

D±. The only requirement is that the 16 CLK pulses finish

before the time tCLKL elapses for the next conversion phase or the

data is lost. From the time tCLKL to tMSB, D± and DCO± are

driven to 0s. Set CLK± to idle low between CLK± bursts.

CLK+

tCYC

CNV+

tCNVH

tCLKL

DCO+

D+

SAMPLE N

SAMPLE N + 1

D–

D15

D14

CLK–

CNV–

DCO–

N – 1

ACQUISITION

tACQ

tDCO

tCLK

tMSB

N – 1

D15

N + 1

D14

N + 1

D13

N + 1

tCLKD

Figure 29. Echoed-Clock Interface Mode Timing Diagram

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