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FG256 数据表(PDF) 2 Page - Microsemi Corporation |
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FG256 数据表(HTML) 2 Page - Microsemi Corporation |
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2 / 166 page  ProASIC3E Flash Family FPGAs II Revision 14 I/Os Per Package1 ProASIC3E Device Status ProASIC3E Devices A3PE600 A3PE1500 3 A3PE3000 3 Cortex-M1 Devices 2 M1A3PE1500 M1A3PE3000 Package I/O Types PQ208 147 65 147 65 147 65 FG256 165 79 –––– FG324 –––– 221 110 FG484 270 135 280 139 341 168 FG676 – – 444 222 – – FG896 –––– 620 310 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E FPGA Fabric User’s Guide to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 4. FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os). 6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of the "G" in the part number. Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions Package PQ208 FG256 FG324 FG484 FG676 FG896 Length × Width (mm\mm) 28 × 28 17 × 17 19 × 19 23 × 23 27 × 27 31 × 31 Nominal Area (mm2) 784 289 361 529 729 961 Pitch (mm) 0.5 1.0 1.0 1.0 1.0 1.0 Height (mm) 3.40 1.60 1.63 2.23 2.23 2.23 ProASIC3E Devices Status M1 ProASIC3E Devices Status A3PE600 Production A3PE1500 Production M1A3PE1500 Production A3PE3000 Production M1A3PE3000 Production |
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