SC172MLTRT datasheet(17/27 Pages) SEMTECH

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Applications Information (continued)

Rate of change of load current is

MAX = maximum load release = 2A

Note that C

OUT is much smaller in this example, 13µF

compared to 99µF based upon a worst-case load re-

lease. To meet the two design criteria of minimum 13µF

and maximum 78mΩ ESR, select one capacitor rated at

22µF and 15mΩ ESR or less.

It is recommended that an additional small capacitor be

placed in parallel with C

OUT in order to filter high frequen-

cy switching noise.

Stability Considerations

Unstable operation is possible with adaptive on-time

controllers, and usually takes the form of double-puls-

ing or ESR loop instability.

Double-pulsing occurs due to switching noise seen at

the FB input or because the FB ripple voltage is too low.

This causes the FB comparator to trigger prematurely af-

ter the minimum off-time has expired. In extreme cases

the noise can cause three or more successive on-times.

Double-pulsing will result in higher ripple voltage at the

output, but in most applications it will not affect opera-

tion. This form of instability can usually be avoided by

providing the FB pin with a smooth, clean ripple signal

that is at least 10mVp-p, which may dictate the need to

0.6A

LOAD

1V)

(1.05V

0.6A

2.26A

OUT

COUT

2.26A

0.511A

LPK

increase the ESR of the output capacitors. It is also im-

perative to provide a proper PCB layout as discussed in

the Layout Guidelines section.

Another way to eliminate doubling-pulsing is to add a

small (~ 10pF) capacitor across the upper feedback resis-

tor, as shown in Figure 8. This capacitor should be left

unpopulated unless it can be confirmed that double-

pulsing exists. Adding the C

TOP capacitor will couple

more ripple into FB to help eliminate the problem. An

optional connection on the PCB should be available for

this capacitor.

VOUT

To FB pin

CTOP

Figure 8 — Capacitor Coupling to FB Pin

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR Re-

quirements section. The best method for checking sta-

bility is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and

ringing. Ringing for more than one cycle after the initial

step is an indication that the ESR should be increased.

One simple way to solve this problem is to add trace re-

sistance in the high current output path. A side effect of

adding trace resistance is a decrease in load regulation.

ESR Requirements

A minimum ESR is required for two reasons. One reason

is to generate enough output ripple voltage to provide

10mVp-p at the FB pin (after the resistor divider) to avoid

double-pulsing.

The second reason is to prevent instability due to insuf-

ficient ESR. The on-time control regulates the valley of

the output ripple voltage. This ripple voltage is the sum

of the two voltages. One is the ripple generated by the

ESR, the other is the ripple due to capacitive charging

)

(

OUT

LOAD

MAX

OUT

LPK

OUT

SC172

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