AT25DF081A datasheet(29/54 Pages) ETC2

29 / 54 page

8715C–SFLSH–1/2013

AT25DF081A

The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin

is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the

device will abort the operation and the user-programmable portion of the OTP Security Register will not be pro-

grammed. The WEL bit in the Status Register will be reset back to the logical “0” state if the OTP Security Register

program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin

being deasserted on uneven byte boundaries, or because the user-programmable portion of the OTP Security

While the device is programming the OTP Security Register, the Status Register can be read and will indicate that

the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting

the tOTPP time to determine if the data bytes have finished programming. At some point before the OTP Security

If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte

user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again.

The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the con-

tents of the buffer will be altered from its previous state when this command is issued.

Figure 10-4. Program OTP Security Register

SCK

MSB

10011011

839

37 38

31 32

29 30

OPCODE

HIGH-IMPEDANCE

AAA

MSB

DDDDDDD

ADDRESS BITS A23-A0

DATA IN BYTE 1

MSB

DDDDDDD

DATA IN BYTE n

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