Bluegiga Technologies Oy

Page 9 of 29

HARDWARE.XML Example (*

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

2

1

0

A7 A6 A5 A4 A3 A2 A1 A0

Alt.1

C

SS MO MI

<usart channel="0" mode="spi_master" alternate="1" ...

Alt.2

MO MI

C

SS

<usart channel="0" mode="spi_master" alternate="2" ...

Alt.1

RT CT TX RX

<usart channel="0" mode="uart" alternate="1" ...

Alt.2

TX RX RT CT

<usart channel="0" mode="uart" alternate="2" ...

Alt.1

MI MO

C

SS

<usart channel="1" mode="spi_master" alternate="1" ...

Alt.2

MO

C

SS

<usart channel="1" mode="spi_master" alternate="2" ...

Alt.1

RX TX RT CT

<usart channel="1" mode="uart" alternate="1" ...

Alt.2

TX RT CT

<usart channel="1" mode="uart" alternate="2" ...

Alt.1

4

3

2

1

0

<timer index="1" alternate="1" ...

Alt.2

3

4

0

<timer index="1" alternate="2" ...

Alt.1

1

0

<timer index="3" alternate="1" ...

Alt.2

0

<timer index="3" alternate="2" ...

Alt.1

<timer index="4" alternate="1" ...

Alt.2

0

<timer index="4" alternate="2" ...

DC DD

5

4

3

2

P1

PERIPHERAL /

FUNCTION

P2

USART 0 SPI (**

R

E

S

E

R

V

E

D

R

E

S

E

R

V

E

D

D

C

D

C

C

O

N

T

R

O

L

DEBUG

OBSSEL

ADC

TIMER 3

TIMER 4

P0

USART 0 UART

USART 1 SPI (**

USART 1 UART

TIMER 1

*) Refer to BLE Configuration Guide for detailed settings

**) SS is the slave select signal when BLE121LR is set as SPI slave. When set as SPI master, any available I/O can be used as chip select signal of

BLE121LR

NOTE: Pins configured as peripheral I/O signals do not have pull-up / -down capability

Table 4: Peripheral I/O Pin Mapping