Copyright © 2013 Future Technology Devices International Limited

14

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.:

FTDI# 259

4 Function Description

The FT240X is a USB to parallel FIFO interface device which simplifies USB implementations and reduces

external component count by fully integrating into the device an MTP memory and an integrated clock

circuit which requires no external crystal. It has been designed to operate efficiently with USB host

controllers by using as little bandwidth as possible when compared to the total USB bandwidth available.

4.1 Key Features

Functional Integration. Fully integrated MTP memory, clock generation, AVCC filtering, power-on-reset

(POR) and LDO regulator.

Configurable CBUS I/O Pin Options. The fully integrated MTP memory allows configuration of the

Control Bus (CBUS) functionality and drive strength selection. There are 2 configurable CBUS I/O options.

The configurable options are defined in section 3.5.

The CBUS lines can be configured with any one of these output options by setting bits in the internal MTP

memory. The device is shipped with the most commonly used pin definitions pre-programmed - see

Section 8 for details.

Asynchronous Bit Bang Mode. In asynchronous bit-bang mode, the eight FIFO lines can be switched

from the regular interface mode to an 8-bit general purpose I/O port. Data packets can be sent to the

device and they will be sequentially sent to the interface at a rate controlled by an internal timer

(equivalent to the baud rate pre-scaler. This option will be described more fully in a separate application

note available from FTDI website (www.ftdichip.com).

Synchronous Bit Bang Mode. The FT240X supports synchronous bit bang mode. This mode differs from

asynchronous bit bang mode in that the interface pins are only read when the device is written to. This

makes it easier for the controlling program to measure the response to an output stimulus as the data

returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website

(www.ftdichip.com) describes this feature.

High Output Drive Option. The parallel FIFO interface and the four FIFO handshake pins can be made

to drive out at three times the standard signal drive level thus allowing multiple devices to be driven, or

devices that require a greater signal drive strength to be interfaced to the FT240X. This option is

configured in the internal MTP memory.

Programmable FIFO RX Buffer Timeout. The FIFO RX buffer timeout is used to flush remaining data

from the receive buffer. This timeout defaults to 16ms, but is programmable over USB in 1ms increments

from 2ms to 255ms, thus allowing the device to be optimised for protocols that require fast response

times from short data packets.

Wake Up Function. If USB is in suspend mode, and remote wake up has been enabled in the internal

MTP memory (it is enabled by default). Strobing the SIWU# pin low for a minimum of 20ms will cause

the FT240X to request a resume from suspend on the USB bus. Normally this can be used to wake up the

host PC from suspend.

Source Power and Power Consumption. The FT240X is capable of operating at a voltage supply

between +3.3V and +5.25V with a nominal operational mode current of 8mA and a nominal USB suspend

mode current of 125µA. This allows greater margin for peripheral designs to meet the USB suspend mode

current limit of 2.5mA. An integrated level converter within allows the FT240X to interface to logic

running at +1.8V to +3.3V (5V tolerant).