13

Dead Time and Propagation Delay Specifications

The ACPL-P302/W302 includes a Propagation Delay Dif-

ference (PDD) specification intended to help designers

minimize “dead time” in their power inverter designs.

Dead time is the time high and low side power transistors

are off. Any overlap in Ql and Q2 conduction will result in

large currents flowing through the power devices from

the high voltage to the low-voltage motor rails. To mini-

mize dead time in a given design, the turn on of LED2

should be delayed (relative to the turn off of LED1) so that

under worst-case conditions, transistor Q1 has just turned

off when transistor Q2 turns on, as shown in Figure 24.

The amount of delay necessary to achieve this condition

is equal to the maximum value of the propagation delay

difference specification, PDD max, which is specified to be

500 ns over the operating temperature range of -40° to

100°C.

Figure 24. Minimum LED Skew for Zero Dead Time.

Figure 25. Waveforms for Dead Time.

Delaying the LED signal by the maximum propagation

delay difference ensures that the minimum dead time is

zero, but it does not tell a designer what the maximum

dead time will be. The maximum dead time is equivalent

to the difference between the maximum and minimum

propagation delay difference specification as shown in

Figure 25. The maximum dead time for the ACPL-P302/

W302 is 1 μs (= 0.5 μs - (-0.5 μs)) over the operating tem-

perature range of –40°C to 100°C.

Note that the propagation delays used to calculate PDD

and dead time are taken at equal temperatures and test

conditions since the optocouplers under consideration

are typically mounted in close proximity to each other and

are switching identical IGBTs.

*PDD = PROPAGATION DELAY DIFFERENCE

NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS

ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

MIN

MAXIMUM DEAD TIME

(DUE TO OPTOCOUPLER)

= PDD* MAX – PDD* MIN

*PDD = PROPAGATION DELAY DIFFERENCE

NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION

DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

PDD* MAX