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PE4308 数据表(PDF) 2 Page - Peregrine Semiconductor Corp.

部件名 PE4308
功能描述  75 廓 RF Digital Attenuator
PDF  11 Pages
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制造商  PEREGRINE [Peregrine Semiconductor Corp.]
网页  http://www.peregrine-semi.com
标志 PEREGRINE - Peregrine Semiconductor Corp.

PE4308 数据表(HTML) 2 Page - Peregrine Semiconductor Corp.

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Product Specification
PE4308
Page 2 of 11
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0162-04
│ UltraCMOS™ RFIC Solutions
Table 2. Pin Descriptions
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Notes: 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 k
Ωresistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 k
Ωresistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on Pin 1 & 3”
paragraph
Figure 14. Pin Configuration (Top View)
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Switching Frequency
The PE4308 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 k
Ω resistor on the inputs to Pin 1 & 3 (see
Figure 5) will eliminate package resonance between
the RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
1
15
14
13
12
11
2
3
4
5
C16
RF1
Data
Clock
LE
GND
Vss/GND
P/S
RF2
C8
20-lead
QFN
4x4mm
Exposed Solder Pad
Pin
No.
Pin
Name
Description
1
C16
Attenuation control bit, 16dB (Note 4).
2
RF1
RF port (Note 1).
3
Data
Serial interface data input (Note 4).
4
Clock
Serial interface clock input.
5
LE
Latch Enable input (Note 2).
6
VDD
Power supply pin.
7
PUP1
Power-up selection bit.
8
PUP2
Power-up selection bit.
9
VDD
Power supply pin.
10
GND
Ground connection.
11
GND
Ground connection.
12
Vss/GND
Negative supply voltage or GND
connection (Note 3)
13
P/S
Parallel/Serial mode select.
14
RF2
RF port (Note 1).
15
C8
Attenuation control bit, 8 dB.
16
C4
Attenuation control bit, 4 dB.
17
C2
Attenuation control bit, 2 dB.
18
GND
Ground connection.
19
C1
Attenuation control bit, 1 dB.
20
N/C
No connect
Paddle
GND
Ground for proper operation
Table 3. Absolute Maximum Ratings
Table 4. Operating Ranges
Symbol
Parameter/Conditions
Min
Max
Units
VDD
Power supply voltage
-0.3
4.0
V
VI
Voltage on any input
-0.3
VDD+
0.3
V
TST
Storage temperature range
-65
150
°C
P
IN
Input power (50
Ω)
+30
dBm
VESD
ESD voltage (Human Body
Model)
500
V
Parameter
Min
Typ
Max
Units
VDD Power Supply
Voltage
2.7
3.0
3.3
V
IDD Power Supply
Current
100
µA
Digital Input High
0.7xVDD
V
Digital Input Low
0.3xVDD
V
Digital Input Leakage
1
µA
Input Power
+24
dBm
Temperature range
-40
85
°C



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