STCD22-0 datasheet(30/39 Pages) STMICROELECTRONICS

30 / 39 page

DC and AC parameters

STCD22x0, STCD23x0, STCD24x0

30/39

Doc ID 15400 Rev 2

CIN

Input capacitance

IOO

Output to output isolation

IOI

Output to input isolation

VENH

Enable voltage high(9)

For EN1-EN4

1.2

VENL

Enable voltage low(9)

For EN1-EN4

0.6

VOPTH

OPT pins voltage high

For OPT1 and OPT2

VCC –0.3

VCC

VOPTL

OPT pins voltage low

For OPT1 and OPT2

GND

GND+0.3

Additive phase noise(3)(10)

at 1 kHz offset

–135

dBc/

at 10 kHz offset

–145

at 100 kHz offset

–150

tJP

Additive period jitter(3)

rms value

tJC

Additive cycle-cycle jitter(3)

rms value

tRECB

Buffer recovery time from off to

STCD2xx0 active

µs

tRECC

STCD2xx0 recovery time from

standby to active (include LDO

wakeup time)

500

µs

tPD

Input to output propagation

delay(3)

Voltage transfer at 50%

3.5

Capacitive load for each channel

Resistive load for each channel

ZOUT

Output impedance for each

channel

Valid for ambient operating temperature: TA = –20 °C to 85 °C; VCC = 2.5 V to 5.1 V; typical TA = 25 °C;

load capacitance = 20 pF, fMCLK = 26 MHz (except where noted).

Total accuracy includes line and load regulation, temperature and process condition. It does not include load and line

transients.

Simulated and determined via design and not 100% tested.

Ripple voltage = 0.1 Vpp.

Clock input voltage level should not exceed VTCXO voltage.

The rise time is measured when clock edge transfers from 10% VCC to 90%VCC. The fall time is measured when clock

edge transfers from 90%VCC to 10%VCC. The output rise/fall time is guaranteed for all input slew rates.

The quiescent current is measured when the enable pins are active, but with no input master clock signal (fMCLK = 0 Hz).

The active current depends on the input master clock Vpp and frequency and the load condition. The typical test condition

is 26 MHz with 1.8 Vpp master clock input, CL = 20 pF.

The test condition is VENH = 1.8 V and VENL = 0 V. When output enables simultaneously, there is no intentional skew in

design between the output clocks.

10. Guaranteed for all input clock slew rates.

Table 10.

DC and AC characteristics (continued)

Sym.

Parameter

Condition(1)

Min

Typ

Max

Unit

STCD22-0 数据表(PDF) 30 Page - STMicroelectronics

STCD22-0 数据表(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

数据表下载