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A3P030 数据表(PDF) 21 Page - Microsemi Corporation |
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A3P030 数据表(HTML) 21 Page - Microsemi Corporation |
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21 / 210 page ![]() ProASIC3 Flash Family FPGAs Re vi s i on 15 2 - 16 Figure 2-4 • Output Buffer Model and Delays (Example) tDP (R) PAD VOL tDP (F) Vtrip Vtrip VOH VCC D 50% 50% VCC 0 V DOUT 50% 50% 0 V tDOUT (R) tDOUT (F) From Array PAD tDP Std Load D CLK Q I/O Interface DOUT D tDOUT tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) |
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