SS

SCK

SI

SO

Don't Care

A6

A5

A4

A3

A2

A1

A0

R/W

0

D7

D6

D5

D4

D3

D2

D1

D0

SS

SCK

SI

SO

A6

A5

A4

A3

A2

A1

A0

1

R/W

D7

D6

D5

D4

D3

D2

D1

D0

SW

BATTERY

LDO

Analog

supply

voltage

LP55281

Digital

supply

voltage

1 PF

100 nF

10 PF

2.8V

LP55281

www.ti.com

SNVS458B – JUNE 2007 – REVISED JUNE 2007

Control Interface

The LP55281 supports two different interface modes:

•

SPI interface (4 wire, serial)

•

SPI INTERFACE

LP55281 is compatible with SPI serial bus specification and it operates as a slave. The transmission consists of

16-bit Write and Read Cycles. One cycle consists of a 7 Address bits, 1 Read/Write (RW) bit and 8 Data bits.

RW bit high state defines a Write Cycle and low a Read Cycle. SO output is normally in high-impedance state

and it is active only when Data is sent out during a Read Cycle. A pull-up resistor may be needed in SO line if a

floating logic signal can cause unintended current consumption in the input circuits where SO is connected. The

Address and Data are transmitted MSB first. The Slave Select signal (SS) must be low during the Cycle

transmission. SS resets the interface when high and it has to be taken high between successive Cycles. Data is

clocked in on the rising edge of the clock signal (SCK), while data is clocked out on the falling edge of SCK.

Figure 18. SPI Write Cycle

Figure 19. SPI Read Cycle

Copyright © 2007, Texas Instruments Incorporated

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