TSB41AB1PHP datasheet(39/71 Pages) TI1

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TSB41AB1

IEEE 1394a2000 ONEPORT CABLE

TRANSCEIVER/ARBITER

SLLS423I − JUNE 2000 − REVISED MARCH 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

APPLICATION INFORMATION

using the TSB41AB1 with a non-IEEE 1394a-2000 link layer

The TSB41AB1 implements the PHY-LLC interface specified in IEEE 1394a-2000. This interface is based upon

the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in older TI

PHY devices. The PHY-LLC interface specified in IEEE 1394a-2000 is completely compatible with the older

Annex J interface.

IEEE 1394a-2000 includes enhancements to the Annex J interface that must be comprehended when using

the TSB41AB1 with a non-IEEE 1394a-2000 LLC device.

D A new LLC service request was added which allows the LLC to enable and disable asynchronous arbitration

accelerations temporarily. If the LLC does not implement this new service request, the arbitration

enhancements should not be enabled (see the EAA bit in PHY register 5).

D The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was

added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not

support multispeed concatenation, multispeed concatenation should not be enabled in the PHY (see the

EMC bit in PHY register 5).

D In order to accommodate the higher transmission speeds expected in future revisions of the standard, IEEE

1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus

request from 7 bits to 8 bits. The new speed codes were carefully selected so that new IEEE 1394a-2000

PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC

devices that use the 2-bit speed codes. The TSB41AB1 correctly interprets both 7-bit bus requests (with

2-bit speed codes) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is

immediately followed by another request (for example, a register read or write request), the TSB41AB1

correctly interprets both requests. Although the TSB41AB1 correctly interprets 8-bit bus requests, a request

with a speed code exceeding S400 results in the TSB41AB1 transmitting a null packet (data-prefix followed

by data-end, with no data in the packet).

More explanation is included in the TI application note IEEE 1394a Features Supported by TI TSB41LV0X

Physical Layer Devices, TI literature number SLLA019.

using the TSB41AB1 with a lower-speed link layer

Although the TSB41AB1 is an S400 capable PHY, it may be used with lower speed LLCs, such as the S200

capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals

on the TSB41AB1 remain unused. Unused Dn terminals should be pulled to ground through 10-k

Ω resistors.

The TSB41AB1 transfers all received packet data to the LLC, even if the speed of the packet exceeds the

capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such

cases. On the rare occasions that the first 16 bits of partial data accepted by such an LLC match the bus ID and

node ID for that node, spurious header CRC or tcode errors may result.

During bus initialization following a bus reset, each PHY transmits a self-ID packet that indicates, among other

information, the speed capability of the PHY. The bus manager (if one exists) builds a speed map from the

collected self-ID packets. This speed map gives the highest possible speed that can be used on the

node-to-node communication paths between every pair of nodes in the network.

TSB41AB1PHP 数据表(PDF) 39 Page - Texas Instruments

TSB41AB1PHP 数据表(HTML) 39 Page - Texas Instruments

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