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MB90P653APF 数据表(PDF) 21 Page - fujitsu semiconductor |
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MB90P653APF 数据表(HTML) 21 Page - fujitsu semiconductor |
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21 / 120 page  21 MB90650A Series s BLOCK DIAGRAM Clock control circuit RAM Interrupt controller 8/16-bit up/down counter/timer 8 bits × 2 channels (16 bits × 1 channel) 8 8 8 8 8 8 8 57 P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P74 P80 to P86 I/O ports CPU F2MC-16L family core ROM Prescaler 16-bit I/O timers IN0, IN1 OUT1 to OUT3 DTP/external interrupt 8 P90 to P97 2 6 IRQ0 to IRQ5 IRQ6, IRQ7 3 PA0 to PA2 5 X0, X1 RST X0A, X1A CKOT (Output switching) × 1 channel UART SIN0 SOT0 SCK0 SIN1, SIN2 SOT1, SOT2 SCK1, SCK2 A/D converter (10 bits) AVCC AVRH, AVRL AVSS ADTG AN0 to AN7 Communications prescaler D/A converter (8 bits) 16-bit input capture × 2 channels 16-bit output compare × 4 channels 16-bit free-run timer × 1 channel AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 2 2 2 2 2 8 DA00, DA01 DVRH DVSS P00 to P07 (8 pins) : Incorporates a pull-up resistor setting register (for input) P10 to P17 (8 pins) : Incorporates a pull-up resistor setting register (for input) P60 to P67 (8 pins) : Incorporates a pull-up resistor setting register (for input) P40 to P46 (7 pins) : Incorporates an open-drain setting register P47, P70 to P72 (4 pins) : Open-drain PPG00, PPG01 PPG10, PPG11 8/16-bit PPG 4 2 2 I2C interface SCL SDA 2 2 2 2 I/O extended serial interface × 2 channels TEST, AD00 to AD15, A16 to A23, ALE, RD, WRL, WRH, HRQ, HAK, RDY, CLK, N.C., MD0 to MD2, VCC, VSS Other pins DTMF DTMF |
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