ADS8341_14 datasheet(13/25 Pages) TI1

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ADS8341

SBAS136D

TABLE IV. Descriptions of the Control Bits within the

Control Byte.

BIT

NAME

DESCRIPTION

Start Bit. Control byte starts with first HIGH bit on

DIN.

6 - 4

A2 - A0

Channel Select Bits. Along with the SGL/DIF bit,

these bits control the setting of the multiplexer input,

see Tables I and II.

SGL/DIF

Single-Ended/Differential Select Bit. Along with bits

A2 - A0, this bit controls the setting of the multiplexer

input, see Tables I and II.

1 - 0

PD1 - PD0

Power-Down Mode Select Bits. See Table V for

details.

PD0 = 1 for external clock mode. After enabling the re-

quired clock mode, only then should the ADS8341 be set to

power-down between conversions (i.e., PD1 = PD0 = 0).

The ADS8341 maintains the clock mode it was in prior to

entering the power-down modes.

External Clock Mode

In external clock mode, the external clock not only shifts

data in and out of the ADS8341, it also controls the A/D

conversion steps. BUSY will go HIGH for one clock period

after the last bit of the control byte is shifted in. Successive-

approximation bit decisions are made and appear at DOUT

on each of the next 16 DCLK falling edges (see Figure 3).

Figure 4 shows the BUSY timing in external clock mode.

Since one clock cycle of the serial clock is consumed with

BUSY going high (while the MSB decision is being made),

16 additional clocks must be given to clock out all 16 bits

of data; thus, one conversion takes a minimum of 25 clock

cycles to fully read the data. Since most microprocessors

communicate in 8-bit transfers, this means that an additional

transfer must be made to capture the LSB.

There are two ways of handling this requirement. One is

shown in Figure 3, where the beginning of the next control

byte appears at the same time the LSB is being clocked out

of the ADS8341. This method allows for maximum through-

put and 24 clock cycles per conversion.

The SGL/DIF bit controls the multiplexer input mode: either

single-ended (HIGH) or differential (LOW). In single-ended

mode, the selected input channel is referenced to the COM

pin. In differential mode, the two selected inputs provide a

differential input. See Tables I and II and Figure 2 for more

information. The last two bits (PD1 - PD0) select the power-

down mode, as shown in Table V. If both inputs are HIGH,

the device is always powered up. If both inputs are LOW, the

device enters a power-down mode between conversions.

When a new conversion is initiated, the device will resume

normal operation instantly—no delay is needed to allow the

device to power up and the very first conversion will be valid.

Clock Modes

The ADS8341 can be used with an external serial clock or

an internal clock to perform the successive-approximation

conversion. In both clock modes, the external clock shifts

data in and out of the device. Internal clock mode is selected

when PD1 is HIGH and PD0 is LOW.

If the user decides to switch from one clock mode to the

other, an extra conversion cycle will be required before the

ADS8341 can switch to the new mode. The extra cycle is

required because the PD0 and PD1 control bits need to be

written to the ADS8341 prior to the change in clock modes.

When power is first applied to the ADS8341, the user must

set the desired clock mode. It can be set by writing PD1

= 1 and PD0 = 0 for internal clock mode or PD1 = 1 and

PD1

PD0

Description

Power-down between conversions. When each

conversion is finished, the converter enters a low

power mode. At the start of the next conversion,

the device instantly powers up to full power. There

is no need for additional delays to assure full

operation and the very first conversion is valid.

Selects Internal Clock Mode

Reserved for Future Use

No power-down between conversions, device al-

ways powered. Selects external clock mode.

TABLE V. Power-Down Selection.

FIGURE 4. Detailed Timing Diagram.

PD0

BDV

CSS

BTR

CSH

DCLK

DOUT

BUSY

DIN

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