TLV2548CPWR datasheet(21/48 Pages) TI1

21 / 48 page

TLV2544, TLV2548

2.7V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER

SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN

SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

recommended operating conditions (continued)

MIN

NOM

MAX

UNIT

Pulse width, SCLK low time, twL(SCLK) (See Figures 16 and 19)

0.4

0.6

SCLKs

Pulse width, SCLK high time, twH(SCLK) (See Figures 16 and 19)

0.4

0.6

SCLKs

Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of

SCLK (FS=1), tsu(DI-SCLK (See Figures 16 and 19)

Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge

of SCLK (FS=1), th(DI-SCLK) (See Figure 16)

Delay time, delay from CS falling edge to SDO valid, td(CSL-DOV)

(See Figures 16 and 19)

Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV) (See Figure 16)

Delay time, delay from SCLK falling edge (FS is

VCC = 4.5 V

SDO = 5 pF

0.5 SCLK

+ 9

Delay time, delay from SCLK falling edge (FS is

active) or SCLK rising edge (FS=1) to SDO valid,

td(SCLK-DOV). (See Figures 16 and 19).

VCC = 4.5 V

SDO = 25 pF

0.5 SCLK

+ 10

td(SCLK-DOV). (See Figures 16 and 19).

For a date code later than xxx, see the date code

information item (3).

VCC = 2.7 V

SDO = 5 pF

0.5 SCLK

+ 18

information item (3).

VCC = 2.7 V

SDO = 25 pF

0.5 SCLK

+ 19

Delay time, delay from 17th SCLK rising edge (FS is active) or the 16th falling edge

(FS=1) to EOC falling edge, td(SCLK-EOCL) (See Figures 16 and 19)

Delay time, delay from 16th SCLK falling edge to INT falling edge (FS =1) or from

the 17th rising edge SCLK to INT falling edge (when FS active), td(SCLK-INTL)

(See Figure 19)

Min t(conv)

µs

Delay time, delay from CS falling edge or FS rising edge to INT rising edge,

td(CSL-INTH) or td(FSH-INTH). See Figures 16, 17, 18 and 19)

Delay time, delay from CS rising edge to CSTART falling edge, td(CSH-CSTARTL)

(See Figures 17 and 18)

100

Delay time, delay from CSTART rising edge to EOC falling edge, td(CSTARTH-EOCL)

(See Figures 17 and 18)

Pulse width, CSTART low time, twL(CSTART) (See Figures 17 and 18)

Min t(sample)

µs

Delay time, delay from CSTART rising edge to CSTART falling edge,

td(CSTARTH-CSTARTL) (See Figure 18)

Max t(conv)

µs

Delay time, delay from CSTART rising edge to INT falling edge, td(CSTARTH-INTL)

(See Figures 17 and 18)

Max t(conv)

µs

Operating free-air temperature, TA

TLV2544C/TLV2548C

°C

Operating free-air temperature, TA

TLV2544I/TLV2548I

−40

°C

TLV2548CPWR 数据表(PDF) 21 Page - Texas Instruments

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TLV2548CPWR 数据表(PDF) 21 Page - Texas Instruments

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