STC3105

14/23

Doc ID 022198 Rev 1

7

7.1

Read and write operations

The interface is used to control and read the current accumulator and registers. It is

interface with a serial data line (SDA) and a serial clock line (SCL).

●

SCL: input clock used to shift data

●

SDA: input/output bidirectional data transfers

A filter rejects the potential spikes on the bus data line to preserve data integrity.

The bidirectional data line supports transfers up to 400 kbit/s (fast mode). The data is shifted

to and from the chip on the SDA line, MSB first.

The first bit must be high (START) followed by the 7-bit device address and the read/write

control bit. Bits DevADDR0 to DevADDR2 are factory-programmable, the default device

address value being 1110 000 (AddrID0 = AddrID1 = AddrID2 = 0). The STC3105 then

sends an acknowledge at the end of an 8-bit long sequence. The next 8 bits correspond to

the register address followed by another acknowledge.

The data field is the last 8-bit long sequence sent, followed by a last acknowledge.

Table 7.

Device address format

b7

b6

b5

b4

b3

b2

b1

b0

1

1

1

0

DevADDR2

DevADDR1

DevADDR0

R/W

Table 8.

Register address format

b7

b6

b5

b4

b3

b2

b1

b0

RegADDR7

RegADDR6

RegADDR5

RegADDR4

RegADDR3

RegADDR2

RegADDR1

RegADDR0

Table 9.

Register data format

b7

b6

b5

b4

b3

b2

b1

b0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0