| 数据搜索系统,热门电子元器件搜索 |
|
ML22563 数据表(PDF) 21 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
ML22563 数据表(HTML) 21 Page - List of Unclassifed Manufacturers |
|
21 / 66 page ![]() FEDL2257X-05 ML22Q573/ML2257X FUNCTIONAL DESCRIPTION Synchronous Serial Interface The CSB, SCK, SI, and SO pins are used to input various commands or read the status of the device. For command input, after inputting a “L” level to the CSB pin, input data through the SI pin with MSB first in sync with the SCK clock signal. The data input through the SI pin is shifted into the LSI in sync with the SCK clock signal, then the command is executed at the eighth pulse of the rising or falling edge of the SCK clock. For status reading, after a “L” level is input to the CSB pin, stauts is output from the SO pin in sync with the SCK clock signal. Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by the signal input through the DIPH pin: - When the DIPH pin is at a “L” level, the data input through the SI pin is shifted into the LSI on the rising edges of the SCK clock pulses and a status signal is output from the SO pin on the falling edges of the SCK clock pulses. - When the DIPH pin is at a “H” level, the data input through the SI pin is shifted into the LSI on the falling edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock pulses. It is possible to input commands even with the CSB pin tied to a “L” level. However, if unexpected pulses caused by noise etc. are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a failure in normal input of command. In addition, the serial interface can be brought back to its initial state by driving the CSB pin at a “H” level. When the CSB pin is at ta “L” level, the status of each channel is output serially in sync with the SCK clock. When the CSB pin is at a ”H” level, the SO pin goes into a high impedance state. CSB SCK SI • C om mand Input Timing: SCK rising edge operation (when D IPH pin = “L” level) D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB ) CSB SCK SI • C om mand Input Timing: SCK falling edge operation (when DIPH pin = “H” level) D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB ) CSB SCK • C om mand Output T iming: SC K falling edge operation (w hen D IPH pin = “L” level) (MSB) (LSB ) CSB SCK Com mand Output Tim ing: SCK ris ing edge operation (when DIPH pi n = “H ” level ) (MSB) (LSB ) SO D7 D6 D5 D4 D3 D2 D1 D0 SO D7 D6 D5 D4 D3 D2 D1 D0 21/66 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |