ML7344C datasheet(21/151 Pages) ETC2

21 / 151 page

FEDL7344C/E/J-04

ML7344C/E/J

21/151

●DIO interface characteristics

Item

Symbol

Condition

Min

Typ.

Max

Unit

DIO Input setup time

TDISU

µs

DIO Input hold time

TDIH

DIO Output hold time

TDOH

DCLK frequency

accuracy in TX (*1)

FDCLK_TX

(*3)

kHz

DCLK frequency

accuracy in RX (*2)

FDCLK_RX

-30

+30

DCLK output duty ratio

(TX)

DDCLK_TX

DCLK output duty ratio

(RX)

DDCLK_RX

Load capacitance

CL=20pF

(*1) DCLK clock frequency in TX mode will be varied depending on the variance of master clock frequency.

(*2) DCLK clock frequency in RX mode will be varied by reproduced clock and its jitter.

(*3) These values are equal to the accuracy of the master clock frequency

NOTE: All timing parameter is defined at voltage level of VDDIO * 20% and VDDIO * 80%.

DCLK

DIO(input)

VALID

FDCLK_TX/ FDCLK_RX

TDISU

TDIH

DIO(output)

VALID

TDOH

ML7344C 数据表(PDF) 21 Page - List of Unclassifed Manufacturers

ML7344C 数据表(HTML) 21 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载