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Product(s)

- Obsolete

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Application information

L4989

12/19

Figure 4.

Reset timing diagram

3.3

Watchdog

A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,

the Reset output pin is set to low. The pulse sequence time can be set within a wide range

with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the

constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is

generated. To prevent this the microcontroller must generate a positive edge during the

discharge of the capacitor before the voltage has reached the threshold Vwlth. In order to

calculate the minimum time t, during which the micro-controller must output the positive

edge, the following equation can be used:

(Vwhth-Vwlth) x Ctw = Icwd x t

Every Wi positive edge switches the current source from discharging to charging. The same

happens when the lower threshold is reached. When the voltage reaches the upper

threshold, Vwhth, the current switches from charging to discharging. The result is a

saw-tooth voltage at the watchdog timer capacitor Ctw.

Figure 5.

Watchdog timing diagram

Wi

Vo

Vcr

Res

<

trr

trr

Tosc

trd = 512 Tosc

Vout_th

Vrhth

Vrlth

Wi

Vcw

Res

Vwlth

Vwhth

twop

twol

Vwlth