STM706T/S/R, STM706P, STM708T/S/R

Pin descriptions

Doc ID 10518 Rev 12

9/32

2.7

PFO

push-pull. PFO pin is not supposed to be forced low by a processor. MR input is gated off

during the period PFO is forced low. Leave open if unused.

Figure 7.

Block diagram (STM706T/S/R and STM706P)

1.

For STM706P only.

Table 3.

Pin description

Pin

Name

Function

STM706P

STM706T/S/R

STM708T/S/R

SO8

TSSOP8

SO8

TSSOP8

SO8

TSSOP8

1

3

1

3

1

3

MR

Push-button reset input

6

8

6

8

—

—

WDI

Watchdog input

8

2

8

2

—

—

WDO

Watchdog output (push-pull)

—

—

7

1

7

1

RST

Active low reset output

7

1

—

—

8

2

RST

Active high reset output

2

4

2

4

2

4

Supply voltage

4

6

4

6

4

6

PFI

Power-fail input

5

7

5

7

5

7

PFO

Power-fail output (push-pull)

3

5

3

5

3

5

Ground

—

—

—

—

6

8

NC

No connect

AI08829

WATCHDOG

TIMER

VRST

WDI

transitional

detector

COMPARE

COMPARE

trec

generator

VPFI

VCC

VCC

PFI

MR

WDI

RST (RST)

(1)

PFO

WDO