ST7232A datasheet(108/157 Pages) STMICROELECTRONICS

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ST7232A

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required informa-

tion for the CPU to process the operation.

11.1.2 Immediate

Immediate instructions have two bytes, the first

byte contains the opcode, the second byte con-

tains the operand value.

11.1.3 Direct

In Direct instructions, the operands are referenced

by their memory address.

The direct addressing mode consists of two sub-

modes:

Direct (short)

The address is a byte, thus requires only one byte

after the opcode, but only allows 00 - FF address-

ing space.

Direct (long)

The address is a word, thus allowing 64 Kbyte ad-

dressing space, but requires 2 bytes after the op-

code.

11.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its

memory address, which is defined by the unsigned

addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three

sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opcode),

and allows 00 - FF addressing space.

Indexed (Short)

The offset is a byte, thus requires only one byte af-

ter the opcode and allows 00 - 1FE addressing

space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte ad-

dressing space and requires 2 bytes after the op-

code.

11.1.5 Indirect (Short, Long)

The required data byte to do the operation is found

by its memory address, located in memory (point-

er).

The pointer address follows the opcode. The indi-

rect addressing mode consists of two sub-modes:

Indirect (short)

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - FF addressing space, and

requires 1 byte after the opcode.

Indirect (long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

Inherent Instruction

Function

NOP

No operation

TRAP

S/W Interrupt

WFI

Wait For Interrupt (Low Pow-

er Mode)

HALT

Halt Oscillator (Lowest Power

Mode)

RET

Sub-routine Return

IRET

Interrupt Sub-routine Return

SIM

Set Interrupt Mask (level 3)

RIM

Reset Interrupt Mask (level 0)

SCF

Set Carry Flag

RCF

Reset Carry Flag

RSP

Reset Stack Pointer

Load

CLR

Clear

PUSH/POP

Push/Pop to/from the stack

INC/DEC

Increment/Decrement

TNZ

Test Negative or Zero

CPL, NEG

1 or 2 Complement

MUL

Byte Multiplication

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

SWAP

Swap Nibbles

Immediate Instruction

Function

Load

Compare

BCP

Bit Compare

AND, OR, XOR

Logical Operations

ADC, ADD, SUB, SBC

Arithmetic Operations

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