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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7232A 数据表(PDF) 26 Page - STMicroelectronics |
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ST7232A 数据表(HTML) 26 Page - STMicroelectronics |
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26 / 157 page  ST7232A 26/157 RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. 6.3.3 External Power-On RESET To start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC net- work connected to the RESET pin. 6.3.4 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 14. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 14. RESET Sequences RESET PIN EXTERNAL WATCHDOG th(RSTL)in RUN WATCHDOG UNDERFLOW tw(RSTL)out RUN RUN RESET RESET SOURCE EXTERNAL RESET WATCHDOG RESET INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH ACTIVE PHASE ACTIVE PHASE 1 |
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