December 2008

Specification Update

13

not equal to 64 bytes, and the entry in the length field is less than 46, but not zero.

Status:

No Fix.

9.

False PCI DMA Completion Notification Causing Data Corruption

Problem:

The PADC1, PADC0, APDC1, and APDC0 complete bits in the PCI_DMACTRL register will

write-1-to-clear (W1C) to the appropriate bit. If another PCI DMA transfer is initiated

after the clear to the PCI_DMACTRL register, an indication of complete will occur before

the DMA transfer has been finished (because the complete bit may not have been

cleared).

• Mask the PADC/APDC enables in the PCI_INTEN register and use software to poll

the EN (bit 31) of the appropriate PCI_ATPDMA0_LENGTH, PCI_PTADMA0_LENGTH

and PCI_ATPDMA1_LENGTH, PCI_PTADMA1_LENGTH register to indicate whether

the DMA transfer was completed.

• If interrupts are preferred, after writing a 1 to clear the appropriate complete bit in

the PCI_DMACTRL register, read the PCI_DMACTRL register back and ensure the

appropriate complete bit was cleared. If not cleared, repeat this step until the

appropriate complete bit is cleared.

Status:

No Fix.

10.

PCI Hangs With a Multiple Inbound Error Condition

Problem:

The PCI controller may lock up if there are multiple errors occurring around two

different inbound PCI transactions.

A lock-up will occur when:

1. An inbound PCI read that targets an internal slave such as the expansion bus or

Queue Manager results in an AHB error that occurs due to the PCI controller

generating an illegal AHB transfer type on the target.

AND

2. A second inbound PCI transfer is started while the first PCI read is still pending and

the second PCI transfer detects a PCI address or data parity error.

lock up.

error is logged (PCI_SRCR.DPE = 1), and the PCI controller retries every inbound

transaction; the system board must reset the IXP43X network processors.

Status:

No Fix.

11.

UART — Break Condition Asserted Too Early If Two Stop Bits are Used

Problem:

The break condition is asserted after the time of the first stop bit, even if two stop bits

are used.

1. A byte consisting only zeros is received.

2. The first stop bit sampling is missed, and only the second one is sampled.

Status:

No Fix.