SC202A

13

The resistor values can be determined using the following

equation.

1

FB

SNS

2

FB

2

FB

1

FB

SET

OUT

R

I

R

R

R

V

V

where V

setting selected by the CTL pins, R

between the output capacitor and the SNS pin, R

resistor between the SNS pin and ground, and I

leakage current into the SNS pin during normal operation.

The current into the SNS pin is typically 1µA, so the last

term of the equation can be neglected if the current

through R

value of 10kΩ or lower will simplify the design. If I

neglected and R

the following equation.

SET

SET

OUT

2

FB

1

FB

V

V

V

R

R

Inserting resistance in the feedback loop will adversely

affect the system’s transient performance if feed-forward

capacitance is not included in the circuit. The circuit in

Figure 1 illustrates how the resistor divider and feed-

forward capacitor can be added to the SC202A

schematic.

SC202A

IN

CTL3

CTL2

CTL1

CTL0

SNS

OUT

GND

Enable

Figure 1 – Application Circuit with External Resistors

The value of feed-forward capacitance needed can be

determined using the following equation.

5

.

0

V

V

V

R

5

.

0

V

V

10

4

C

SET

SET

OUT

1

FB

2

OUT

SET

6

FF

To simplify the design, it is recommended to program the

output setting to 1.0V, use resistor values smaller than

10kΩ, and include a feed-forward capacitance calculated

with the previous equation. If the output voltage is set to

1.0V, the previous equation reduces to the following

equation.

1

V

R

5

.

0

V

10

8

C

OUT

1

FB

2

OUT

6

FF

Example:

An output voltage of 1.3V is desired, but this is not a pro-

grammable option. What external component values for

Figure 1 are needed?

Solution: To keep the circuit simple, set R

current into the SNS pin can be neglected and set the

CTL3-0 pins to 0010 (1.0V setting). The necessary compo-

nent values for this situation are shown by the following

equations.

k

3

V

V

V

R

R

SET

SET

OUT

2

FB

1

FB

nF

69

.

5

1

V

R

5

.

0

V

10

8

C

OUT

1

FB

2

OUT

6

FF

PWM Operation

Normal PWM operation occurs when the output load

current exceeds the PSAVE threshold. In this mode, the

PMOS high side switch is activated with the duty cycle

required to produce the output voltage programmed by

the CTL pins. An internal synchronous NMOS rectifier

eliminates the need for an external Schottky diode on

the LX pin. The duty cycle (percentage of time PMOS is

active) increases as V

voltage regulation. As the input voltage approaches the

programmed output voltage, the duty cycle approaches

100% (PMOS always on) and the device enters a pass-

through mode until the input voltage increases or the

load decreases enough to allow PWM switching to

resume.

Power Save Mode Operation

When the load current decreases below the PSAVE

threshold, PWM switching stops and the device auto-

matically enters PSAVE mode. This threshold varies

depending on the input voltage and output voltage

Applications Information (continued)