Timing Diagrams

Data output

Keyboard data input

HT82K28A

16

February 16, 2000

(1 )

(3 )

(4 )

I/O

In h i b i t

2nd

CL K

10t h

CL K

11t h

CL K

D A T A

St a r t B i t

B i t 0

Pa r i t y B i t

St o p B i t

T7

T8

T9

(5 )

( 7 )

CL K

(6 )

T i m i n g P ar am et e r

w h en t h e au x i l i a r y de v i ce s a m p l e s D A T A

T7

D u r a ti o n o f C L K i n a cti v e

T8

D u r a ti o n o f C L K a cti v e

T 9

T i m e f r o m i n a cti v e to a cti v e C L K tr a n s i ti o n , u s e d to ti m e

Mi n / Ma x

1s t

CL K

(2 )

9t h

CL K

(8 )

(5 )

30/ 50 m se c

30/ 50 m se c

5/ 25 m se c

(1 )

( 3 )

(3 )

(3 )

(3 )

( 4 )

1s t

CL K

2nd

CL K

10t h

CL K

11t h

CL K

D A T A

S t a r t B i t

B i t 0

P a r i ty B i t

S t o p B i t

T5

T3

T4

T1

T2

(2 )

(5 ) ( 7 )

CL K

(6 )

T i m i n g P ar am et e r

t h e a u x i l i a r y dev i ce d oes not s t a r t a not he r t r an s m i s s i o n

T1

D A T A t r a ns i t i o n t o t he f a l l i ng e dge o f C L K

T2

R i s i n g edg e of C LK t o D A T A t r a n s i t i o n

T3

D u r a ti o n o f C L K i n a cti v e

T4

D u r a ti o n o f C L K a cti v e

T5

T i m e to a u x i l i a r y d e v i c e i n h i b i t a fte r cl o ck 1 1 to e n s u r e

Mi n / Ma x

5/ T 4 - 5 m se c

5/ 25 m se c

30/ 5 0 m se c

> 0 / 50 m se c

30/ 5 0 m se c