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HT9032B 数据表(PDF) 7 Page - Holtek Semiconductor Inc |
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HT9032B 数据表(HTML) 7 Page - Holtek Semiconductor Inc |
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7 / 10 page  HT9032 7 April 6, 2000 Functional Description The HT9032 is designed to be the physical layer demodulator for products targeted for the caller ID market. The data signaling interface should conform to Bell 202, which is described as fol- lows: · Analog, phase coherent, frequency shift keying · Logical 1 (Mark)=1200+/-12Hz · Logical 0 (Space)=2200+/-22Hz · Transmission rate=1200bps · Data application=serial, binary, asynchronous The interface should be arranged to allow sim- ple data transmission from the terminating central office, to the CPE (Customer Premises Equipment), only when the CPE is in an on-hook state. The data will be transmitted in the silent period between the first and second power ring before a voice path is established. The transmission level from the terminating C.O. will be -13.5dBm+/-1.0. The worst case at- tenuation through the loop is expected to be -20dB. The receiver therefore, should have a sensitivity of approximately -34.5dBm to han- dle the worst case installations. The ITU-T V.23 is also using the FSK signaling scheme to transmit data in the general switched tele- phone network. For mode 2 of the V.23, the modulation rate and characteristic frequencies are listed below: · Analog, phase coherent, frequency shift keying · Logical 1 (Mark)=1300Hz · Logical 0 (Space)=2100Hz · Transmission rate=1200bps Since the band pass filter of the HT9032 can pass the V.23 signal, hence the HT9032 also can demodulate the V.23 signal. Ring detection The data will be transmitted in the silent pe- riod between the first and second power ring be- fore a voice path is established. The HT9032 should first detect a valid ring and then per- form the FSK demodulation. The typical ring detection circuit of the HT9032 is depicted be- low. The power ring signal is first rectified through a bridge circuit and then sent to a re- sistor network that attenuates the incoming power ring. The values of resistors and capaci- tor given in the figure have been chosen to pro- vide a sufficient voltage at RDET1 pin to turn on the Schmitt Trigger input with approxi- mately a 40 Vrms or greater power ring input from tip and ring. When VT+ of the Schmitt is exceeded, the NMOS on the pin RTIME will be driven to saturation discharging capacitor on RTIME. This will initialize a partial power up, with only the portions of the part involved with the ring signal analysis enabled, including RDET2 pin. With RDET2 pin enabled, a portion of the power ring above 1.2V is fed to the ring analysis circuit. Once the ring signal is quali- fied, the RDET pin will be sent low. P o we r Up Logi c I n t e r nal P o we r Up Logi c Ri n g A nal y s i s Ci r c u i t 1. 2V RDE T 2 RDE T RT I M E V DD 0. 2 m F 27 0k W PD W N RDE T 1 47 0k W 18k W 15k W To B r i dge |
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