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IL715 数据表(PDF) 7 Page - List of Unclassifed Manufacturers |
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IL715 数据表(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 18 page ![]() IL715/IL716/IL717 7 NVE Corporation 11409 Valley View Road, Eden Prairie, MN 55344-3617 Phone: (952) 829-9217 Fax: (952) 829-9189 www.IsoLoop.com ©NVE Corporation 5 Volt Electrical Specifications (Tmin to Tmax unless otherwise stated) Parameters Symbol Min. Typ. Max. Units Test Conditions Input Quiescent Supply Current IL715 and IL715-3 IDD1 24 30 µA IL715-1 350 500 µA IL716 3.6 5 mA IL717 1.8 2.5 mA Output Quiescent Supply Current IL715 IDD2 7.2 10 mA IL716 3.6 5 mA IL717 5.4 7.5 mA Logic Input Current II −10 10 µA Logic High Output Voltage VOH VDD − 0.1 VDD V IO = −20 µA, VI = VIH 0.8 x VDD 0.9 x VDD IO = −4 mA, VI = VIH Logic Low Output Voltage VOL 0 0.1 V IO = 20 µA, VI = VIL 0.5 0.8 IO = 4 mA, VI = VIL Switching Specifications (VDD = 5V) Maximum Data Rate 100 110 Mbps CL = 15 pF Pulse Width(7) PW 10 ns 50% Points, V O Propagation Delay Input to Output (High to Low) tPHL 10 15 ns CL = 15 pF Propagation Delay Input to Output (Low to High) tPLH 10 15 ns CL = 15 pF Pulse Width Distortion(2) PWD 2 3 CL = 15 pF Pulse Jitter(10) tJ 100 ps CL = 15 pF Propagation Delay Skew(3) tPSK 4 6 ns CL = 15 pF Output Rise Time (10%−90%) tR 1 3 ns CL = 15 pF Output Fall Time (10%−90%) tF 1 3 ns CL = 15 pF Common Mode Transient Immunity (Output Logic High or Logic Low)(4) |CMH|,|CML| 30 50 kV/µs V CM = 1500 VDC t TRANSIENT = 25 ns Channel-to-Channel Skew t CSK 2 3 ns CL = 15 pF Dynamic Power Consumption(6) 200 340 μA/Mbps per channel Magnetic Field Immunity(8) (VDD2= 5V, 3V<VDD1<5.5V) Power Frequency Magnetic Immunity HPF 2800 3500 A/m 50Hz/60Hz Pulse Magnetic Field Immunity HPM 4000 4500 A/m tp = 8µs Damped Oscillatory Magnetic Field HOSC 4000 4500 A/m 0.1Hz – 1MHz Cross-axis Immunity Multiplier(9) KX 2.5 Notes (apply to both 3.3 V and 5 V specifications): 1. Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee performance. 2. PWD is defined as |t PHL − tPLH|. %PWD is equal to PWD divided by pulse width. 3. t PSK is the magnitude of the worst-case difference in tPHL and/or tPLH between devices at 25°C. 4. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD 2. CML is the maximum common mode input voltage that can be sustained while maintaining V O < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 5. Device is considered a two terminal device: pins 1–8 shorted and pins 9–16 shorted. 6. Dynamic power consumption is calculated per channel and is supplied by the channel’s input side power supply. 7. Minimum pulse width is the minimum value at which specified PWD is guaranteed. 8. The relevant test and measurement methods are given in the Electromagnetic Compatibility section on p. 7. 9. External magnetic field immunity is improved by this factor if the field direction is “end-to-end” rather than to “pin-to-pin” (see diagram on p. 7). 10. 66,535-bit pseudo-random binary signal (PRBS) NRZ bit pattern with no more than five consecutive 1s or 0s; 800 ps transition time. |
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