2

0311J–EPROM–4/11

Atmel AT27C4096

2.

Pin configurations

Note:

Both GND pins must be

connected

3.

System considerations

Switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. Unless

accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance.

At a minimum, a 0.1µF, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This

capacitor should be connected between the V

Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7µF bulk electrolytic

capacitor should be utilized, again connected between the V

close as possible to the point where the power supply is connected to the array.

Figure 3-1.

Block diagram

Pin name

Function

A0 - A17

Addresses

O0 - O15

Outputs

CE

Chip enable

OE

Output enable

NC

No connect

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

O12

O11

O10

O9

O8

GND

NC

O7

O6

O5

O4

A13

A12

A11

A10

A9

GND

NC

A8

A7

A6

A5

44-lead PLCC

Top view

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

VPP

CE

O15

O14

O13

O12

O11

O10

O9

O8

GND

O7

O6

O5

O4

O3

O2

O1

O0

OE

VCC

A17

A16

A15

A14

A13

A12

A11

A10

A9

GND

A8

A7

A6

A5

A4

A3

A2

A1

A0

40-lead PDIP

Top view