GDC21D301A datasheet(16/35 Pages) HYNIX

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GDC21D301A

Interrupt Flag 2 (0x002)

When

interrupt

condition

occurs,

the

corresponding bit in Interrupt Flag registers are

asserted 1. Whenever a bit in the Interrupt Flag is 1,

the corresponding bit in Interrupt Mask registers is

set to 1, the Ien bit in the Instruction register to 1,

and the GDC21D301A asserts DSP_INT, the

external interrupt signal. Note that the occurrence

of an interrupt condition always causes the

corresponding bit in Interrupt Flag registers to be

set, even if the condition is disabled(i.e., the

corresponding bit in Interrupt Mask registers is

set to 0).

Interrupt Flag 1, 2 registers

are cleared by the

Host whenever they are read, and DSP_INT is

deasserted.

In the GDC21D301A, Slk and Sdr is added to

indicate the state of Sync. The GDC21D301A first

searches Sync byte from transport stream. If the

device

succeeds

finding

0x47,

writes

Slk(Sync_lock) bit in Interrupt flag 2 register. Until

sync is detected, Sdr flag maintains active high

state, so the host processor can monitor whether

Sync(0x47) is detected or not.

All bits except Slk and Sdr are set when packet is

matched to PID register.

FIELD

BITS

DESCRIPTION

VALUES

DEFAULT

Slk

Sync_lock

Sdr

Sync_drop

Psc

13:12

PES_scrambling_control

Ppr

PES_priority

Dai

data_alignment_indicator

Cpr

Ooc

original_or_copy

Pdf

7:6

PTS_DTS_flag

Esf

ESCR_flag

Erf

ES_rate_flag

Dtf

DSM_trick_mode_flag

Acf

additional_copy_info_flag

Crf

PES_CRC_flag

Pef

PES_extension_flag

Interrupt Mask 1 (0x004)

All bits respectively correspond with each ones in

Interrupt Flag 1 register.

1 = Interrupt enabled

Interrupt Mask 2 (0x006)

All bits respectively correspond with each ones in

Interrupt Flag 2 register.

1 = Interrupt enabled

Psc

Ppr Dai Cpr Ooc

Pdf

Esf

Erf

Dtf Acf Crf Pef

Sdr

Slk

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