6

ICS1886

Input Pin Descriptions

Transmit Data Input (TD+ and TD-) For normal operation

this differential input is transferred to the TX± output

through a PECL buffer. In loopback testing mode, this input

is multiplexed to the input of the device clock recovery

section.

Receive Data Input (RX+ and RX-) The clock recovery

and data regenerator from the receive buffer are driven from

this PECL input. During loopback testing mode this input is

ignored.

Clock Select (CS0 and CS1) Selects the operating

frequency according to Table 1. Internal pull-up resistors

set both inputs high when left unconnected.

Carrier Detect (CD~) Active low input which forces the

VCO to free run. Upon receipt of a loss of input signal

(such as from an optical-to-elec-trical transducer), the

internal phase-lock loop will free-run at the selected

operating frequency. Also, when asserted, CD will set the

lock output low.

Loop Timing Mode (LT~) Active low input which routes

the recovered receive clock to the TC± outputs as well as

the RC± outputs. Forces the transmit clock to be ‘loop-

timed’ to the system clock derived from the incoming data.

Loopback Mode (LB~) Active low input which causes the

clock recovery PLL to operate using the transmit TD± input

data and ignore the receive RX± data. Utilized for system

loopback testing.

External Crystal or Reference Clock (REF+ and REF-)

This oscillator input can be driven from either a

fundamental mode crystal or a stable reference. For either

frequency. See Table 1 for more information.

ECL (TX+ and TX-) This differential output is buffered TD±

data. This output remains active during loopback mode.

Transmit Clock Differential ECL (TC+ and TC-)

Differential output clock used by the PDH/ATM processor

for clocking out transmit data. This clock can be derived

from either an independent clock source or from the

recovered data clock (system loop time mode).

Receive Data Differential ECL (RD+ and RD-) The

regenerated differential data derived from the serial data

input. In loopback mode this data is regenerated from the

transmit data input (TD±). This data is phase-aligned with

the negative edge of the RC clock output.

Receive Clock Differential ECL (RC+ and RC-) The

differential clock recovered with the internal clock recov-

ery PLL. In loopback mode this clock is recovered from the

transmit data (TD±) input. This clock is phase-aligned with

the RD data output.

Lock/Loss Detect (LOCK) Set high when the clock

recovery PLL has locked onto the incoming data. Set low

when there is no incoming data, which in turn causes the

PLL to free-run. This signal can be used to indicate or

‘alarm’ the next receive stage that the incoming serial data

has stopped.

Output Description

The differential output drivers are current mode and are de-

signed to drive resistive terminations in a complementary

fash-ion. The outputs are current-sinking only, with the

amount of sink current programmable via the IPRGx pins.

The sink current is equal to four times the IPRGx current.

For most applications, a resistor from VDD to IPRGx will

set the current to the necessary precision. IPRG1 supplies

the current mirror for the TX± output. IPRG2 supplies the

current mirrors for the RD±, RC± and TC± outputs.

The differential PECL output pins are incapble of sourcing

resistors for each of these lines. R1 is a pull-up resistor

con-nected from the PECL output to VSS. R1 and R2 are

electrically in parallel from an AC stand point. If we pick a

target imped-ance of 50Ω for our transmission line

impedance, a value of 62Ω for R1 and a value of 300Ω for

R2 would yield a Thevenin equivalent characteristic

compatible with PECL circuits.

that will cause the output FET’s to sink an appropriate

up a sink current of 19 milliamperes would guarantee this

through out output terminating resistors. As this is

controlled by a 4/1 current mirror, 4.75mA into Iprg should

Iprg should work fine.