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ICS1892Y 数据表(PDF) 98 Page - Integrated Circuit Systems |
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ICS1892Y 数据表(HTML) 98 Page - Integrated Circuit Systems |
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98 / 148 page  ICS1892, Rev. D, 2/26/01 February 26, 2001 98 Chapter 8 Management Register Set ICS1892 Data Sheet © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. 8.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1892 operations. Note: 1. For an explanation of acronyms used in Table 8-20, see Chapter 1, “Abbreviations and Acronyms”. 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits. † The default is the state of this pin at reset. Table 8-21. Extended Control Register (register [0x13]) Bit Definition When Bit = 0 When Bit = 1 Ac- cess SF De- fault Hex 19.15 Node/Repeater Mode Node mode Repeater mode RO – NOD/ REP† – 19.14 Hardware/Software Mode Hardware mode Software mode RO – HW/ SW† 19.13 Remote Fault No faults detected Remote fault detected RO – 0 19.12 ICS reserved Read unspecified Read unspecified RW – 0 19.11 ICS reserved Read unspecified Read unspecified RW – 0 0 19.10 ICS reserved Read unspecified Read unspecified RO – 0 19.9 ICS reserved Read unspecified Read unspecified RW – 0 19.8 ICS reserved Read unspecified Read unspecified RW – 0 19.7 ICS reserved Read unspecified Read unspecified RW – 0 0 19.6 ICS reserved Read unspecified Read unspecified RW – 0 19.5 ICS reserved Read unspecified Read unspecified RW – 0 19.4 ICS reserved Read unspecified Read unspecified RW – 0 19.3 ICS reserved Read unspecified Read unspecified RW – 0 3 19.2 ICS reserved Read unspecified Read unspecified RW – 0 19.1 Automatic 10Base-T Power Down Do not automatically power down Power down automatically RW – 1 19.0 Automatic 100Base-TX Power Down Do not automatically power down Power down automatically RW – 1 |
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