Bit 3 - FIFO 25% Full (read only)

This bit goes high after 4 words (or 8 bytes) have been

loaded into the FIFO, and low again when 5 words (or

10 bytes) may be loaded into the FIFO. There is no

interrupt associated with this bit directly.

Bit 4 - FIFO 50% Full (read only)

This bit goes high after 8 words (or 16 bytes) have been

loaded into the FIFO, and low again when 9 words (or

18 bytes) may be loaded into the FIFO. There is no

interrupt associated with this bit directly.

Bit 5 - FIFO 75% Full (read only)

This bit goes high after 12 words (or 24 bytes) have

been loaded into the FIFO, and low again when 13

words (or 26 bytes) may be loaded into the FIFO. There

is no interrupt associated with this bit directly.

Bit 6 - FIFO DIR (read only)

This bit goes high when a single word (or two bytes)

may be written to the FIFO. There is no interrupt

associated with this bit directly. Note that this bit resets

to a one because when the FIFO is reset it is forced to

be “empty,” and hence is ready to accept data.

Bit 7 - FIFO DOR (read only)

This bit goes high when a single word (or two bytes)

may be read from the FIFO. There is no interrupt

associated with this bit directly.

IR9D Record FIFO IRQ Mode

Bits 7:4 - reserved

Bit 3 - FIFO IRQ Enable (RFIE)

This bit enables the various FIFO capacity thresholds

to generate interrupts (as RECIRQ) when one. When

zero, this bit prevents FIFO capacity IRQ generation

when operating in DMA mode, which only needs

RTCIRQ.

Bits 2:0 - FIFO Ready IRQ Mode Selection

This register defines FIFO utilization for both DMA

and I/O mode data transfers. In I/O mode, it is used to

generate interrupts (RECIRQ) when the FIFO capacity

reaches a predefined point. For DMA transfers, it sig-

nals the DMA logic to request a transfer at those same

predefined points. By programming the Record DMA

Burst Count appropriately, the FIFO may be easily kept

near the desired capacity.

The following table describes the selections available:

Bits

2:0

Source

Notes

000

DIR

Ready to take 1 word from DSP

001

EMPTY 75% Ready to take 13 words from DSP

010

EMPTY 50% Ready to take 9 words from DSP

011

EMPTY 25% Ready to take 5 words from DSP

100

DOR

Ready to provide 1 word to HOST

101

FULL 25%

Ready to provide 4 words to HOST

110

FULL 50%

Ready to provide 8 words to HOST

111

FULL 75%

Ready to provide 12 words

Note that for byte transfers (RDMA16=0), the numbers listed

above should be doubled.

This must be programmed before the FIFO is enabled. It may

be changed while the FIFO is enabled if necessary. This register

is cleared by MCR, but not by RFE low.

IR9E reserved

IR9F reserved

Miscellaneous Registers

IRA0 Digital Master Volume

Bits 7:0 - Volume

This value is used to scale all values that are output from

the DSP to the DAC. It may be written while the DSP

is running.

The value written is interpreted as to give a log scale

output response of 0.1875dB per step. The value for

nominal (0dB attenuation) is E0h. A value of FFh gives

5.8125dB of gain. Note that any value above E0h may

result in digital saturation of the internal 16 bit data

value.

ICS2002

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