ICS2008B

8

ICS2008B Rev D 4/05/05

Video Control Register IR32

GENLOCK ENABLE — When set to one, this bit enables

the genlock circuits to sync to the selected video input signal.

When reset to 0, the video sync will “freewheel,” generating

video timing from the internal oscillator. The freewheel mode

would be selected when striping LTC to allow synchroni-

zation with a MIDI sequencer or other strictly timed audio

source.

VTRES — When set to one, this bit clears the video timing

counters to dot zero of line 1 of field 1. This is useful when the

video is free running, not genlocked and LTC sync needs to be

synchronized to an event such as the CLICK input.

VSYNCSEL — When set to one, this bit selects the video

input source from Video2 (Y2) to be the SYNC source for the

internal video timing. Otherwise, when reset to zero, Video1

(Y1) is selected.

VITCSEL — When set to one, this bit selects the video input

source from Video2 (Y2) to be the VITC time code source for

the VITC receiver. Otherwise, when reset to zero, Video1

(Y1) is selected.

VOUTSEL — When set to one, this bit selects the video

input source from Video2 (Y2, C2) to be output on the video

outputs (YOUT, COUT). When reset to zero, Video1 (Y1,

C1) are selected.

VID1_S — When set to one, this bit causes the Video1 source

to be treated as S-Video. Otherwise, when cleared to zero, the

Video1 source is treated as composite video.

VID2_S — When set to one, this bit causes the Video2 source

to be treated as S-Video. Otherwise, when cleared to zero, the

Video2 source is treated as composite video.

VITC Read Line Select Registers IR30-IR31

As with the VITC Write Line Register, these registers allow

control of the individual redundant VITC read lines. The

processor can also reprogram these dynamically to allow for

scanning of VITC code when the source lines are unknown.

Read Line – Selects the line from which VITC code is to be

read within each field. It works identically to the Write Line

in that the video line selected is the number in this register

plus 10.

Auto line scanning is enabled by writing a 1Fh to the Read

Line field. This causes the VITC reader to search for time

code. If VITC Read Line 1 is set to search, it starts with line

10 and quits when it finds a valid time code or when it reaches

line 41. Searching with VITC Read Line 2 starts after VITC

Read Line 1. In the case of searching for both VITC Read

Lines 1 and 2, VITC Read Line 2 starts searching after the

first valid time code has been found. However, if VITC Read

Line 1 is set to a specific line, VITC Read Line 2 starts after

that specified line regardless of whether valid time code was

received. In any case, the search terminates after line 41.

CRCERR — This bit is reset to zero when a valid VITC code

has been received. It is valid from the end of the selected

video line until the end of the selected line in the next field.

NOCODE — This bit is set when a framing error occurs in

the VITC code, i.e. not all the bits of the code were received

by the time the end of the video line occurred. Both CRCERR

and NOCODE must be zero to qualify a VITC code.

Video Control Register

GENLOCK ENABLE (1-lock, 0-freewheel)

VTRES - Video Timing Reset (1-reset)

VSYNCEL - Video SYNC Source Select

VITCSEL - VITC Source Select

VOUTSEL - Video Output Select

VID1_S - Video1 S-Video Select

VID2_S - Video2 S-Video Select

PAL/NTSC (1-PAL, 0-NTSC)

7

6

5

4

3

2

1

0

IR32

VITC Read Line 1

Read Line 10-40 (N+10)

CRCERR (1-error, 0-OK) (r/o)

NOCODE (1-no code, 0-code) (r/o)

VITC Read Enable (1-enable)

IR30

7

6

5

4

3

2

1

0

VITC Read Line 2

Read Line 10-40 (N+10)

CRCERR (1-error, 0-OK) (r/o)

NOCODE (1-no code, 0-code) (r/o)

VITC Read Enable (1-enable)

IR31

7

6

5

4

3

2

1

0