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ICS2510C 数据表(PDF) 4 Page - Integrated Circuit Systems

部件名 ICS2510C
功能描述  3.3V Phase-Lock Loop Clock Driver
PDF  7 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS2510C 数据表(HTML) 4 Page - Integrated Circuit Systems

  ICS2510C Datasheet HTML 1Page - Integrated Circuit Systems ICS2510C Datasheet HTML 2Page - Integrated Circuit Systems ICS2510C Datasheet HTML 3Page - Integrated Circuit Systems ICS2510C Datasheet HTML 4Page - Integrated Circuit Systems ICS2510C Datasheet HTML 5Page - Integrated Circuit Systems ICS2510C Datasheet HTML 6Page - Integrated Circuit Systems ICS2510C Datasheet HTML 7Page - Integrated Circuit Systems  
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ICS2510C
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
Fclk
Input clock frequency
25
175
MHz
Input clock frequency
duty cycle
40
60
%
Stabilization time
After power up
1
ms
Timing requirements over recommended ranges of supply
voltage and operating free-air temperature
Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be
Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not
Electrical Characteristics - Input & Supply
T
A = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2V
DD+0.3
V
Input Low Voltage
V
IL
V
SS-0.3
0.8
V
Input High Current
I
IH
V
IN = VDD
0.1
100
uA
Input Low Current
I
IL
V
IN = 0 V;
19
50
uA
Operating current
I
DD1
C
L = 0 pF; FIN @ 66M
140
170
mA
Input Capacitance
C
IN
1
Logic Inputs
4
pF
Output Capacitance
C
O
1
Logic Outputs
8
pF
1Guarenteed by design, not 100% tested in production.



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