ICS507-01/02

PECL Clock Synthesizer

MDS 507 C

3

Revision 042600

Printed 11/13/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RAT

TINGS (stressees be ond these can perm

manentl damaage the device)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

-0.5

VDD+0.5

V

Clock Output

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperaturre

ICS507M-0x

0

70

°C

ICS507M-0xI

-40

85

°C

Soldering Temperature

Max of 20 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VD

DD = 5.0 V unlless otherwise noted)

Operating Voltage, VDD

3.0

5.5

V

Input High Voltage, VIH

ICLK only

VDD/2 + 1

VDD/2

V

Input Low Voltage, VIL

ICLK only

VDD/2

VDD/2-1

V

Input High Voltage, VIH

S0, S1

VDD-0.5

V

Input Low Voltage, VIL

S0, S1

VDD+0.5

V

Output High Voltage, VOH

Note 2

VDD-1.2

V

Output Low Voltage, VOL

Note 2

VDD-2.0

V

IDD Operating Suppl Current, note 3

No Load, 155.52MHz

67

mA

Internal Cr stal Capacitance, X1 and X2

Pins 1, 8

26

pF

Input Capacitance

S0, S1

4

pF

AC CHARACTERISTICS (VD

DD = 5.0 V unlless otherwise noted)

Input Crystal Frequency

5

27

MHz

Input Clock Frequency

5

52

MHz

Output Frequency, ICS507-01

0 to 70°C VDD = 5.0 V

10

200

MHz

0 to 70°C VDD = 3.3 V

10

156

MHz

Output Frequency, ICS507-01I

-40 to 85°C VDD = 3.3 V or 5.0 V

10

125

MHz

Output Frequency, ICS507-02I

0 to 70°C VDD = 5.0 V

125

200

MHz

0 to 70°C VDD = 3.3 V

125

200

MHz

-40 to 85°C VDD = 3.3 V or 5.0 V

125

160

MHz

Output Clock Duty Cycle

49

51

%

PLL Bandwidth

10

kHz

Absolute Clock Period Jitter

Deviation from mean

±75

ps

One Sigma Clock Period Jitter

20

ps

Electrical Specifications

Notes:

1) All typical values are at 5.0 V and 25°C unless otherwise noted.

2) VOH and VOL can be set by the external resistor values on the PECL outputs.

3) IDD includes the current through the external resistors, which can be modified.

4) The phase relationship between input and output can change at power up. For a fixed phase relationship, see one of the

ICS zero delay buffers.