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ICS508 数据表(PDF) 5 Page - Integrated Circuit Systems

部件名 ICS508
功能描述  PECL to CMOS Converter
PDF  5 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS508 数据表(HTML) 5 Page - Integrated Circuit Systems

  ICS508 Datasheet HTML 1Page - Integrated Circuit Systems ICS508 Datasheet HTML 2Page - Integrated Circuit Systems ICS508 Datasheet HTML 3Page - Integrated Circuit Systems ICS508 Datasheet HTML 4Page - Integrated Circuit Systems ICS508 Datasheet HTML 5Page - Integrated Circuit Systems  
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ICS508
PECL to CMOS Converter
MDS 508 C
5
Revision 012400
Printed 11/13/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
While the information presented herein has been checked for both accuracy and reliability, ICS assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support
devices or critical medical instruments.
Ordering Information
Part/Order Number
Marking
Package
Temperature
ICS508M
ICS508M
8 pin SOIC
0 to 70 °C
ICS508MT
ICS508M
8 pin SOIC on tape and reel
0 to 70 °C
ICS508MI
ICS508I
8 pin SOIC
-40 to +85 °C
ICS508MIT
ICS508I
8 pin SOIC on tape and reel
-40 to +85 °C
ICS508-DWF
-
Die on uncut, probed wafers
0 to 70 °C
ICS508-DPK
-
Tested die in waffle pack
0 to 70 °C
External Components
The ICS508 requires two 0.01µF decoupling capacitors to be connected between VDDP and GND and
between VDDC and GND. They must be connected close to the ICS508 to minimize lead inductance. A
33
Ω series terminating resistor can be used next to the CLK pin.
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
B
D
EH
e
A1
C
A
h x 45°
L
INDEX
AREA
12
8 pin SOIC
Inch
hes
Millim
meters
Symbol
Min
Max
Min
Max
A
0.0532
0.0688
1.35
1.75
A1
0.0040
0.0098
0.10
0.24
B
0.0130
0.0200
0.33
0.51
C
0.0075
0.0098
0.19
0.24
D
0.1890
0.1968
4.80
5.00
E
0.1497
0.1574
3.80
4.00
e
.050 BSSC
1.27 BSSC
H
0.2284
0.2440
5.80
6.20
h
0.0099
0.0195
0.25
0.50
L
0.0160
0.0500
0.41
1.27



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