ICS512

LOCO™ PLL Clock Multiplier

MDS 512 C

3

Revision 061900

Printed 11/13/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com

Electrical Specifications

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (stresses bee ond these can permaneentl damage tthe device)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

-0.5

VDD+0.5

V

Clock Output

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

ICS512MI only

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3V unless ootherwise noted)

Operating Voltage, VDD

3

5.5

V

Input High Voltage, VIH, ICLK only

ICLK (Pin 1)

(VDD/2)+1

VDD/2

V

Input Low Voltage, VIL, ICLK only

ICLK (Pin 1)

VDD/2

(VDD/2)-1

V

Input High Voltage, VIH

S0, S1

VDD-0.5

V

Input Low Voltage, VIL

S0, S1

0.5

V

Output High Voltage, VOH, CMOS high

IOH=-8mA

VDD-0.4

V

Output High Voltage, VOH

IOH=-12mA

2.4

V

Output Low Voltage, VOL

IOL=12mA

0.4

V

IDD Operating Supply Current, 20 MHz crystal No Load, 100MHz

9

mA

Short Circuit Current

CLK output

±70

mA

Input Capacitance, S1, S0

Pins 6, 7

4

pF

AC CHARACTERISTICS (VDD = 3.3V unless ootherwise noted)

Input Frequency, crystal input

5

27

MHz

Input Frequency, clock input

2

50

MHz

Output Frequency, VDD = 4.5 to 5.5V

0 to +70 °C

14

200

MHz

Note 1

-40 to +85 °C

14

160

MHz

Output Frequency, VDD = 3.0 to 3.6V

0 to +70 °C

14

160

MHz

Note 1

-40 to +85 °C

14

145

MHz

Output Clock Rise Time

0.8 to 2.0V

1

ns

Output Clock Fall Time

2.0 to 0.8V

1

ns

Output Clock Duty Cycle

at VDD/2

45

49 to 51

55

%

Absolute Clock Period Jitter

Deviation from mean

±200

ps

One Sigma Clock Period Jitter

80

ps

Note 1: The phase relationship between input and output clocks can change at power up. For a fixed phase relationship, see the ICS570

or the ICS527.