ICS527-01

Clock Slicer™

User Configurable Zero Delay Buffer

MDS 527-01 B

5

Revision 020801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com

Typical Example

The following connection diagram shows the implementation of the example from the previous section.

This will generate a 50 MHz clock synchronously with a 40 MHz input. A SYNC pulse is desired and the

1x output drive is selected.

VDD

Note that the feedback is done AFTER the series termination resistor.

This will give the following waveforms:

40 MHz ICLK

50 MHz CLK1

SYNC CLK2

R5

R6

DIV2

S0

S1

VDD

ICLK

FBIN

GND

GND

R4

R3

R2

R1

R0

VDD

CLK1

CLK2

OECLK2

2XDRIVE

F0

F1

F2

F6

F5

F4

F3

PDTS

50 MHz

SYNC

33

Ω

33

Ω

40 MHz

0.01 µF

0.01 µF