ICS541

PLL Clock Divider

MDS 541 B

3

Revision 082500

Printed 11/14/00

Integrated Circuit Systems, Inc. •525 Race Street• San Jose•CA• 95126• (408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

Electrical Specifications

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

-0.5

VDD+0.5

V

Clock Output

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

C

Soldering Temperature

Max of 10 seconds

260

C

Storage temperature

-65

150

C

DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)

DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)

Operating Voltage, VDD

3

5.5

V

Input High Voltage, VIH, ICLK only, Note 1

ICLK (Pin 1)

(VDD/2)+1

V

Input Low Voltage, VIL, ICLK only, Note 1

ICLK (Pin 1)

(VDD/2)-1

V

Input High Voltage, VIH

S0, S1, OE

2

V

Input Low Voltage, VIL

S0, S1, OE

0.8

V

Output High Voltage, VOH

IOH=-25mA

2.4

V

Output Low Voltage, VOL

IOL=25mA

0.4

V

Output High Voltage, VOH, CMOS level

IOH=-4mA

VDD-0.4

V

IDD Operating Supply Current, 80 in, 40+20 out No Load, 5.0V

15

mA

IDD Operating Supply Current, 40 in, 40+20 out No Load, 3.3V

8

mA

Short Circuit Current

Each Output

±70

mA

Input Capacitance, S1, S0, OE

Pins 4, 5, 6

4

pF

AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)

AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)

Input Frequency, clock input

at VDD = 5V

4

156

MHz

Input Frequency, clock input

at VDD = 3.3V

4

135

MHz

Skew of output clocks

rising edges at VDD/2

500

ps

Output Clock Rise Time

0.8 to 2.0V

1

ns

Output Clock Fall Time

2.0 to 0.8V

1

ns

Output Clock Duty Cycle

at VDD/2

45

49 to 51

55

%

Note 1: CMOS level input; nominal trip point is VDD/2.